From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
x86@kernel.org, Matt Fleming <matt.fleming@intel.com>,
Will Auld <will.auld@intel.com>,
Kanaka Juvva <kanaka.d.juvva@intel.com>
Subject: [patch 3/6] x86, perf, cqm: Remove pointless spinlock from state cache
Date: Tue, 19 May 2015 00:00:53 -0000 [thread overview]
Message-ID: <20150518235150.001006529@linutronix.de> (raw)
In-Reply-To: 20150518234114.574556332@linutronix.de
[-- Attachment #1: x86-perf-cqm-remove-pointless-spinlock.patch --]
[-- Type: text/plain, Size: 2730 bytes --]
struct intel_cqm_state is a strict per cpu cache of the rmid and the
usage counter. It can never be modified from a remote cpu.
The 3 functions which modify the content: start, stop and del (del
maps to stop) are called from the perf core with interrupts disabled
which is enough protection for the per cpu state values.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
Index: linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ linux/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -17,11 +17,16 @@ static unsigned int cqm_max_rmid = -1;
static unsigned int cqm_l3_scale; /* supposedly cacheline size */
struct intel_cqm_state {
- raw_spinlock_t lock;
u32 rmid;
int cnt;
};
+/*
+ * The cached intel_cqm_state is strictly per cpu and can never be
+ * updated from a remote cpu. Both functions which modify the state
+ * (intel_cqm_event_start and intel_cqm_event_stop) are called with
+ * interrupts disabled, which is sufficient for the protection.
+ */
static DEFINE_PER_CPU(struct intel_cqm_state, cqm_state);
/*
@@ -963,15 +968,12 @@ static void intel_cqm_event_start(struct
{
struct intel_cqm_state *state = this_cpu_ptr(&cqm_state);
u32 rmid = event->hw.cqm_rmid;
- unsigned long flags;
if (!(event->hw.cqm_state & PERF_HES_STOPPED))
return;
event->hw.cqm_state &= ~PERF_HES_STOPPED;
- raw_spin_lock_irqsave(&state->lock, flags);
-
if (state->cnt++)
WARN_ON_ONCE(state->rmid != rmid);
else
@@ -984,21 +986,17 @@ static void intel_cqm_event_start(struct
* Technology component.
*/
wrmsr(MSR_IA32_PQR_ASSOC, rmid, 0);
-
- raw_spin_unlock_irqrestore(&state->lock, flags);
}
static void intel_cqm_event_stop(struct perf_event *event, int mode)
{
struct intel_cqm_state *state = this_cpu_ptr(&cqm_state);
- unsigned long flags;
if (event->hw.cqm_state & PERF_HES_STOPPED)
return;
event->hw.cqm_state |= PERF_HES_STOPPED;
- raw_spin_lock_irqsave(&state->lock, flags);
intel_cqm_event_read(event);
if (!--state->cnt) {
@@ -1013,8 +1011,6 @@ static void intel_cqm_event_stop(struct
} else {
WARN_ON_ONCE(!state->rmid);
}
-
- raw_spin_unlock_irqrestore(&state->lock, flags);
}
static int intel_cqm_event_add(struct perf_event *event, int mode)
@@ -1257,7 +1253,6 @@ static void intel_cqm_cpu_prepare(unsign
struct intel_cqm_state *state = &per_cpu(cqm_state, cpu);
struct cpuinfo_x86 *c = &cpu_data(cpu);
- raw_spin_lock_init(&state->lock);
state->rmid = 0;
state->cnt = 0;
next prev parent reply other threads:[~2015-05-19 0:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-19 0:00 [patch 0/6] x86, perf, cqm: Cleanups and preparation for RDT/CAT Thomas Gleixner
2015-05-19 0:00 ` [patch 1/6] x86, perf, cqm: Document PQR MSR abuse Thomas Gleixner
2015-05-19 11:53 ` Matt Fleming
2015-05-27 10:02 ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-05-19 0:00 ` [patch 2/6] x86, perf, cqm: Use proper data type Thomas Gleixner
2015-05-19 8:58 ` Matt Fleming
2015-05-19 13:03 ` Thomas Gleixner
2015-05-27 10:03 ` [tip:perf/core] perf/x86/intel/cqm: Use proper data types tip-bot for Thomas Gleixner
2015-05-19 0:00 ` Thomas Gleixner [this message]
2015-05-19 9:13 ` [patch 3/6] x86, perf, cqm: Remove pointless spinlock from state cache Matt Fleming
2015-05-19 10:51 ` Peter Zijlstra
2015-05-27 10:03 ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-06-05 18:13 ` [patch 3/6] x86, perf, cqm: " Juvva, Kanaka D
2015-05-19 0:00 ` [patch 4/6] x86, perf, cqm: Avoid pointless msr write Thomas Gleixner
2015-05-19 9:17 ` Matt Fleming
2015-05-27 10:03 ` [tip:perf/core] perf/x86/intel/cqm: Avoid pointless MSR write tip-bot for Thomas Gleixner
2015-05-19 0:00 ` [patch 5/6] x86, perf, cqm: Remove useless wrapper function Thomas Gleixner
2015-05-19 9:18 ` Matt Fleming
2015-05-27 10:04 ` [tip:perf/core] perf/x86/intel/cqm: " tip-bot for Thomas Gleixner
2015-05-19 0:00 ` [patch 6/6] x86, perf, cqm: Add storage for closid and cleanup struct intel_pqr_state Thomas Gleixner
2015-05-19 11:54 ` Matt Fleming
2015-05-19 12:59 ` Thomas Gleixner
2015-05-27 10:04 ` [tip:perf/core] perf/x86/intel/cqm: Add storage for 'closid' and clean up 'struct intel_pqr_state' tip-bot for Thomas Gleixner
2015-05-19 7:42 ` [patch 0/6] x86, perf, cqm: Cleanups and preparation for RDT/CAT Peter Zijlstra
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