[tip:perf/core] perf/x86/intel/cqm: Avoid pointless MSR write

tip-bot for Thomas Gleixner
2015-05-27T10:04:27Z

Commit-ID: 0bac237845e203dd1439cfc571b1baf1b2274b3b
Gitweb: http://git.kernel.org/tip/0bac237845e203dd1439cfc571b1baf1b2274b3b
Author: Thomas Gleixner <tglx@linutronix.de>
AuthorDate: Tue, 19 May 2015 00:00:55 +0000
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 27 May 2015 09:17:40 +0200

perf/x86/intel/cqm: Avoid pointless MSR write

If the usage counter is non-zero there is no point to update the rmid
in the PQR MSR.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Matt Fleming <matt.fleming@intel.com>
Cc: Kanaka Juvva <kanaka.d.juvva@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: Will Auld <will.auld@intel.com>
Link: http://lkml.kernel.org/r/20150518235150.080844281@linutronix.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/perf_event_intel_cqm.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
index 63391f8..2ce69c0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -974,10 +974,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode)

event->hw.cqm_state &= ~PERF_HES_STOPPED;

- if (state->cnt++)
- WARN_ON_ONCE(state->rmid != rmid);
- else
+ if (state->cnt++) {
+ if (!WARN_ON_ONCE(state->rmid != rmid))
+ return;
+ } else {
WARN_ON_ONCE(state->rmid);
+ }

state->rmid = rmid;
/*