From: Thierry Reding <thierry.reding@gmail.com>
To: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Cc: swarren@wwwdotorg.org, gnurou@gmail.com, pdeschrijver@nvidia.com,
mturquette@linaro.org, rjw@rjwysocki.net,
viresh.kumar@linaro.org, pwalmsley@nvidia.com, vinceh@nvidia.com,
pgaikwad@nvidia.com, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, tuomas.tynkkynen@iki.fi
Subject: Re: [PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks
Date: Tue, 19 May 2015 17:22:10 +0200 [thread overview]
Message-ID: <20150519152208.GB28161@ulmo.nvidia.com> (raw)
In-Reply-To: <555B517F.4080506@kapsi.fi>
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On Tue, May 19, 2015 at 06:06:39PM +0300, Mikko Perttunen wrote:
> On 05/19/2015 05:59 PM, Thierry Reding wrote:
> >On Tue, May 19, 2015 at 02:39:27PM +0300, Mikko Perttunen wrote:
> >>This patch allows SoC-specific CAR initialization routines to register
> >>their own reset_assert and reset_deassert callbacks with the common Tegra
> >>CAR code. If defined, the common code will call these callbacks when a
> >>reset control with number >= num_periph_banks * 32 is attempted to be asserted
> >>or deasserted respectively. Numbers greater than or equal to num_periph_banks * 32
> >>are used to avoid clashes with low numbers that are automatically mapped to
> >>standard CAR reset lines.
> >>
> >>Each SoC with these special resets should specify the defined reset control
> >>numbers in a device tree header file.
> >
> >This is looking pretty good, but I think we can simplify a wee bit
> >more...
> >
> >>Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
> >>Acked-by: Michael Turquette <mturquette@linaro.org>
> >>---
> >> drivers/clk/tegra/clk.c | 39 +++++++++++++++++++++++++++++++--------
> >> drivers/clk/tegra/clk.h | 3 +++
> >> 2 files changed, 34 insertions(+), 8 deletions(-)
> >>
> >>diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> >>index 41cd87c..c093ed9 100644
> >>--- a/drivers/clk/tegra/clk.c
> >>+++ b/drivers/clk/tegra/clk.c
> >>@@ -49,7 +49,6 @@
> >> #define RST_DEVICES_L 0x004
> >> #define RST_DEVICES_H 0x008
> >> #define RST_DEVICES_U 0x00C
> >>-#define RST_DFLL_DVCO 0x2F4
> >> #define RST_DEVICES_V 0x358
> >> #define RST_DEVICES_W 0x35C
> >> #define RST_DEVICES_X 0x28C
> >>@@ -79,6 +78,11 @@ static struct clk **clks;
> >> static int clk_num;
> >> static struct clk_onecell_data clk_data;
> >>
> >>+/* Handlers for SoC-specific reset lines */
> >>+static int (*special_reset_assert)(unsigned long);
> >>+static int (*special_reset_deassert)(unsigned long);
> >>+static int special_reset_num;
> >
> >I think we can get rid of this if we...
> >
> >>+
> >> static struct tegra_clk_periph_regs periph_regs[] = {
> >> [0] = {
> >> .enb_reg = CLK_OUT_ENB_L,
> >>@@ -152,19 +156,29 @@ static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
> >> */
> >> tegra_read_chipid();
> >>
> >>- writel_relaxed(BIT(id % 32),
> >>- clk_base + periph_regs[id / 32].rst_set_reg);
> >>+ if (id < periph_banks * 32) {
> >>+ writel_relaxed(BIT(id % 32),
> >>+ clk_base + periph_regs[id / 32].rst_set_reg);
> >>+ return 0;
> >>+ } else if (id < periph_banks * 32 + special_reset_num) {
> >>+ return special_reset_assert(id);
> >>+ }
> >
> >... pass id - periph_banks * 32 into special_reset_assert(). Oh, but
> >then...
>
> The reason I don't subtract periph_banks * 32 is because this way the code
> in the SoC-specific callback can just include the dt-bindings header and use
> the same defines used in the device tree.
Indeed, you're right. Now if
static int special_reset_num;
could be turned into
static unsigned int num_special_reset;
I'd be happy to take this into the Tegra clock tree.
Thierry
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next prev parent reply other threads:[~2015-05-19 15:22 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-13 14:58 [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 01/17] clk: tegra: Add binding for the Tegra124 DFLL clocksource Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 02/17] clk: tegra: Add library for the DFLL clock source (open-loop mode) Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 03/17] clk: tegra: Add closed loop support for the DFLL Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 04/17] clk: tegra: Add functions for parsing CVB tables Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks Mikko Perttunen
2015-05-19 11:39 ` [PATCH v10 " Mikko Perttunen
2015-05-19 11:46 ` Mikko Perttunen
2015-05-19 14:59 ` Thierry Reding
2015-05-19 15:06 ` Mikko Perttunen
2015-05-19 15:22 ` Thierry Reding [this message]
2015-05-20 6:27 ` [PATCH v11 " Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124 Mikko Perttunen
2015-05-19 11:43 ` [PATCH v10 " Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 07/17] clk: tegra: Add Tegra124 DFLL clocksource platform driver Mikko Perttunen
2015-05-26 18:17 ` Kevin Hilman
2015-05-13 14:58 ` [PATCH v9 08/17] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 09/17] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 10/17] ARM: tegra: Add the DFLL to Tegra124 device tree Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1 Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 12/17] cpufreq: tegra124: Add device tree bindings Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 13/17] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 14/17] cpufreq: Add cpufreq driver for Tegra124 Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 15/17] ARM: tegra: Add entries for cpufreq on Tegra124 Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 16/17] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 17/17] ARM: tegra: enable Tegra124 cpufreq driver by default Mikko Perttunen
2015-05-13 22:47 ` [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Rafael J. Wysocki
2015-05-14 6:15 ` Mikko Perttunen
2015-05-14 20:15 ` Rafael J. Wysocki
2015-05-15 2:09 ` Viresh Kumar
2015-05-15 5:16 ` Mikko Perttunen
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