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From: Jason Cooper <jason@lakedaemon.net>
To: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org, devicetree@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 05/15] irqchip: mips-gic: register IRQ domain with MIPS_GIC_IRQ_BASE
Date: Fri, 22 May 2015 17:27:02 +0000	[thread overview]
Message-ID: <20150522172702.GC19834@io.lakedaemon.net> (raw)
In-Reply-To: <1432309875-9712-6-git-send-email-paul.burton@imgtec.com>

On Fri, May 22, 2015 at 04:51:04PM +0100, Paul Burton wrote:
> On Malta, some IRQs are still referenced by hardcoded numbers relative
> to MIPS_GIC_IRQ_BASE. When gic_init is called to register the GIC
> without using device tree the irqbase argument allows this base to be
> used. When the GIC is probed using device tree however the base is not
> specified. This leads to conflicts between the GIC interrupts and other
> interrupt controllers.
> 
> TODO: convert Malta (& SEAD3) to drop the hardcoded numbers instead

This will never be seen again. :-P  Why not just go ahead and do it as separate
patch(es) in this series?

thx,

Jason.

> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> ---
> 
>  drivers/irqchip/irq-mips-gic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index 57f09cb..697f340 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -858,7 +858,7 @@ static int __init gic_of_init(struct device_node *node,
>  		write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
>  	gic_present = true;
>  
> -	__gic_init(gic_base, gic_len, cpu_vec, 0, node);
> +	__gic_init(gic_base, gic_len, cpu_vec, MIPS_GIC_IRQ_BASE, node);
>  
>  	return 0;
>  }
> -- 
> 2.4.1
> 

  reply	other threads:[~2015-05-22 17:27 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-22 15:50 [PATCH 00/15] MIPS Malta DT Conversion Paul Burton
2015-05-22 15:51 ` [PATCH 01/15] MIPS: define GCR_GIC_STATUS register fields Paul Burton
2015-05-22 15:51 ` [PATCH 02/15] MIPS: include errno.h for ENODEV in mips-cm.h Paul Burton
2015-05-22 15:51 ` [PATCH 03/15] MIPS: malta: basic DT plumbing Paul Burton
2015-05-22 15:51 ` [PATCH 04/15] MIPS: i8259: DT support Paul Burton
2015-05-22 15:51 ` [PATCH 05/15] irqchip: mips-gic: register IRQ domain with MIPS_GIC_IRQ_BASE Paul Burton
2015-05-22 17:27   ` Jason Cooper [this message]
2015-05-22 15:51 ` [PATCH 06/15] MIPS: malta: probe interrupt controllers via DT Paul Burton
2015-05-22 15:51 ` [PATCH 07/15] MIPS: remove [SR]ocIt(2) IRQ handling code Paul Burton
2015-05-22 15:51 ` [PATCH 08/15] of_serial: support for UARTs on I/O ports Paul Burton
2015-05-26 13:53   ` Peter Hurley
2015-05-22 15:51 ` [PATCH 09/15] MIPS: malta: probe UARTs using DT Paul Burton
2015-05-22 15:51 ` [PATCH 10/15] MIPS: malta: probe RTC via DT Paul Burton
2015-05-22 15:51 ` [PATCH 11/15] MIPS: malta: probe pflash " Paul Burton
2015-05-22 15:51 ` [PATCH 12/15] MIPS: malta: remove fw_memblock_t abstraction Paul Burton
2015-05-22 15:51 ` [PATCH 13/15] MIPS: malta: remove nonsense memory limit Paul Burton
2015-05-22 15:51 ` [PATCH 14/15] MIPS: malta: setup RAM regions via DT Paul Burton
2015-10-29  4:39   ` Rob Herring
2015-05-22 15:51 ` [PATCH 15/15] MIPS: malta: setup post-I/O hole RAM on non-EVA Paul Burton
2015-05-25  7:59 ` [PATCH 00/15] MIPS Malta DT Conversion Rob Landley
2015-05-25 13:29   ` Paul Burton

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