public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
From: Paul Burton <paul.burton@imgtec.com>
To: Hauke Mehrtens <hauke@hauke-m.de>
Cc: <linux-mips@linux-mips.org>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Lars-Peter Clausen <lars@metafoo.de>,
	Mark Rutland <mark.rutland@arm.com>,
	Pawel Moll <pawel.moll@arm.com>,
	"Ralf Baechle" <ralf@linux-mips.org>,
	Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org>,
	Joshua Kinard <kumba@gentoo.org>,
	"Leonid Yegoshin" <Leonid.Yegoshin@imgtec.com>,
	Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>,
	<linux-kernel@vger.kernel.org>,
	Markos Chandras <markos.chandras@imgtec.com>,
	Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Subject: Re: [PATCH v5 36/37] MIPS: ingenic: initial JZ4780 support
Date: Tue, 26 May 2015 08:25:48 +0100	[thread overview]
Message-ID: <20150526072548.GS13811@NP-P-BURTON> (raw)
In-Reply-To: <5563019A.2050702@hauke-m.de>

[-- Attachment #1: Type: text/plain, Size: 1519 bytes --]

On Mon, May 25, 2015 at 01:03:54PM +0200, Hauke Mehrtens wrote:
> > diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
> > index 1bed3cb..510fc0d 100644
> > --- a/arch/mips/jz4740/setup.c
> > +++ b/arch/mips/jz4740/setup.c
> > @@ -83,6 +83,9 @@ arch_initcall(populate_machine);
> >  
> >  const char *get_system_type(void)
> >  {
> > +	if (config_enabled(CONFIG_MACH_JZ4780))
> > +		return "JZ4780";
> > +
> >  	return "JZ4740";
> >  }
> 
> Shouldn't this be provided by device tree, now it depends on your kernel
> config.

At some point, when the kernel is generic enough that one binary works
across multiple SoCs, yes definitely. Even better might be to detect it
at runtime. The kernel can currently only be built for a single SoC
though, so the code as-is works just fine & gets things working on the
CI20 without making an already lengthy patchset longer than it needs to
be.

> > diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
> > index 9172553..7ab47fe 100644
> > --- a/arch/mips/jz4740/time.c
> > +++ b/arch/mips/jz4740/time.c
> > @@ -102,7 +102,12 @@ static struct clock_event_device jz4740_clockevent = {
> >  	.set_next_event = jz4740_clockevent_set_next,
> >  	.set_mode = jz4740_clockevent_set_mode,
> >  	.rating = 200,
> > +#ifdef CONFIG_MACH_JZ4740
> >  	.irq = JZ4740_IRQ_TCU0,
> > +#endif
> > +#ifdef CONFIG_MACH_JZ4780
> > +	.irq = JZ4780_IRQ_TCU2,
> > +#endif
> >  };
> 
> same here.

Same response :)

Thanks,
    Paul

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

  reply	other threads:[~2015-05-26  7:26 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-24 15:11 [PATCH v5 00/37] JZ4780 & CI20 support Paul Burton
2015-05-24 15:11 ` [PATCH v5 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix Paul Burton
2015-05-24 15:11 ` [PATCH v5 02/37] devicetree/bindings: add Qi Hardware " Paul Burton
2015-05-24 15:11 ` [PATCH v5 03/37] MIPS: JZ4740: introduce CONFIG_MACH_INGENIC Paul Burton
2015-05-24 15:11 ` [PATCH v5 04/37] MIPS: ingenic: add newer vendor IDs Paul Burton
2015-05-24 15:11 ` [PATCH v5 05/37] MIPS: JZ4740: require & include DT Paul Burton
2015-05-24 15:11 ` [PATCH v5 06/37] MIPS: irq_cpu: declare irqchip table entry Paul Burton
2015-05-26 15:38   ` Ralf Baechle
2015-05-24 15:11 ` [PATCH v5 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT Paul Burton
2015-05-24 15:17   ` Sergei Shtylyov
2015-05-24 22:37     ` [PATCH v6 " Paul Burton
2015-05-24 15:11 ` [PATCH v5 08/37] MIPS: JZ4740: use generic plat_irq_dispatch Paul Burton
2015-05-24 15:11 ` [PATCH v5 09/37] MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c Paul Burton
2015-05-24 15:11 ` [PATCH v5 10/37] devicetree: document Ingenic SoC interrupt controller binding Paul Burton
2015-05-24 15:11 ` [PATCH v5 11/37] MIPS: JZ4740: probe interrupt controller via DT Paul Burton
2015-05-24 15:11 ` [PATCH v5 12/37] MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT Paul Burton
2015-05-24 15:11 ` [PATCH v5 13/37] MIPS: JZ4740: register an irq_domain for the interrupt controller Paul Burton
2015-05-24 15:11 ` [PATCH v5 14/37] MIPS: JZ4740: drop intc debugfs code Paul Burton
2015-05-24 15:11 ` [PATCH v5 15/37] MIPS: JZ4740: remove jz_intc_base global Paul Burton
2015-05-24 15:11 ` [PATCH v5 16/37] MIPS: JZ4740: support >32 interrupts Paul Burton
2015-05-24 15:11 ` [PATCH v5 17/37] MIPS: JZ4740: define IRQ numbers based on number of intc IRQs Paul Burton
2015-05-24 15:11 ` [PATCH v5 18/37] MIPS: JZ4740: read intc base address from DT Paul Burton
2015-05-24 15:11 ` [PATCH v5 19/37] MIPS: JZ4740: avoid JZ4740-specific naming Paul Burton
2015-05-24 15:11 ` [PATCH v5 20/37] MIPS: JZ4740: support newer SoC interrupt controllers Paul Burton
2015-05-24 15:11 ` [PATCH v5 21/37] irqchip: move Ingenic SoC intc driver to drivers/irqchip Paul Burton
2015-05-24 15:11 ` [PATCH v5 22/37] MIPS: JZ4740: call jz4740_clock_init earlier Paul Burton
2015-05-24 15:11 ` [PATCH v5 23/37] MIPS: JZ4740: replace use of jz4740_clock_bdata Paul Burton
2015-05-24 15:11 ` [PATCH v5 24/37] devicetree: add Ingenic CGU binding documentation Paul Burton
2015-05-24 15:11 ` [PATCH v5 25/37] clk: ingenic: add driver for Ingenic SoC CGU clocks Paul Burton
2015-05-24 15:11 ` [PATCH v5 26/37] MIPS,clk: migrate JZ4740 to common clock framework Paul Burton
2015-05-24 15:11 ` [PATCH v5 27/37] MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu Paul Burton
2015-05-24 15:11 ` [PATCH v5 28/37] MIPS, clk: move jz4740 UDC auto suspend functions " Paul Burton
2015-05-24 15:11 ` [PATCH v5 29/37] MIPS, clk: move jz4740 clock suspend, resume " Paul Burton
2015-05-24 15:11 ` [PATCH v5 30/37] clk: ingenic: add JZ4780 CGU support Paul Burton
2015-06-03 23:32   ` Michael Turquette
2015-05-24 15:11 ` [PATCH v5 31/37] MIPS: JZ4740: remove clock.h Paul Burton
2015-05-24 15:11 ` [PATCH v5 32/37] MIPS: JZ4740: only detect RAM size if not specified in DT Paul Burton
2015-05-24 15:11 ` [PATCH v5 33/37] devicetree: document Ingenic SoC UART binding Paul Burton
2015-05-24 15:11 ` [PATCH v5 34/37] serial: 8250_ingenic: support for Ingenic SoC UARTs Paul Burton
2015-05-31 21:49   ` Greg Kroah-Hartman
2015-05-24 15:11 ` [PATCH v5 35/37] MIPS: JZ4740: use Ingenic SoC UART driver Paul Burton
2015-05-24 15:11 ` [PATCH v5 36/37] MIPS: ingenic: initial JZ4780 support Paul Burton
2015-05-25 11:03   ` Hauke Mehrtens
2015-05-26  7:25     ` Paul Burton [this message]
2015-05-24 15:11 ` [PATCH v5 37/37] MIPS: ingenic: initial MIPS Creator CI20 support Paul Burton

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20150526072548.GS13811@NP-P-BURTON \
    --to=paul.burton@imgtec.com \
    --cc=Leonid.Yegoshin@imgtec.com \
    --cc=andreas.herrmann@caviumnetworks.com \
    --cc=dengcheng.zhu@imgtec.com \
    --cc=devicetree@vger.kernel.org \
    --cc=galak@codeaurora.org \
    --cc=hauke@hauke-m.de \
    --cc=ijc+devicetree@hellion.org.uk \
    --cc=kumba@gentoo.org \
    --cc=lars@metafoo.de \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mips@linux-mips.org \
    --cc=mark.rutland@arm.com \
    --cc=markos.chandras@imgtec.com \
    --cc=pawel.moll@arm.com \
    --cc=ralf@linux-mips.org \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox