Re: [Patch V1 2/3] x86, mce: Add infrastructure required to support LMCE

[Borislav Petkov <bp@alien8.de>]

On Fri, May 29, 2015 at 09:28:01AM -0700, Ashok Raj wrote:
> Initialization and handling for LMCE
> - boot time option to disable LMCE for that boot instance
> - Check for capability via IA32_MCG_CAP
> - provide ability to enable/disable LMCE on demand.
> 
> See http://www.intel.com/sdm Volume 3 System Programming Guide, Chapter 15
> for more information on MSR's and documentation on Local MCE.
> 
> Signed-off-by: Ashok Raj <ashok.raj@intel.com>
> ---
>  Documentation/x86/x86_64/boot-options.txt |  3 ++
>  arch/x86/include/asm/mce.h                |  5 +++
>  arch/x86/kernel/cpu/mcheck/mce.c          |  3 ++
>  arch/x86/kernel/cpu/mcheck/mce_intel.c    | 75 +++++++++++++++++++++++++++++++
>  4 files changed, 86 insertions(+)

> +static bool lmce_supported(void)
> +{
> +	u64 cap, feature_ctl;
> +	bool lmce_bios_support, retval;
> +
> +	if (mca_cfg.lmce_disabled)
> +		return false;
> +
> +	rdmsrl(MSR_IA32_MCG_CAP, cap);
> +	rdmsrl(MSR_IA32_FEATURE_CONTROL, feature_ctl);
> +
> +	/*
> +	 * BIOS should indicate support for LMCE by setting
> +	 * bit20 in IA32_FEATURE_CONTROL. without which touching
> +	 * MCG_EXT_CTL will generate #GP fault.
> +	 */
> +	lmce_bios_support = ((feature_ctl & (FEATURE_CONTROL_LMCE_BITS)) ==
> +			(FEATURE_CONTROL_LMCE_BITS));
> +
> +	/*
> +	 * MCG_CAP should indicate both MCG_SER_P and MCG_LMCE_P
> +	 */
> +	cap = ((cap & MCG_CAP_LMCE_BITS) == (MCG_CAP_LMCE_BITS));

No need for those local definitions of MSR bits. Simply do:

	if (feature_ctl & (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE_SUPPORT_ENABLED) !=
			  (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE_SUPPORT_ENABLED))
		return false;

Same with cap:

	if (cap & (.. | ..) != ( .. | ..))
		return false;

	return true;

Also, shorten those bit definitions.


> +	retval = (cap && lmce_bios_support);
> +
> +	return retval;
> +}
> +
>  bool mce_intel_cmci_poll(void)
>  {
>  	if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE)
> @@ -405,6 +437,49 @@ static void intel_init_cmci(void)
>  	cmci_recheck();
>  }
>  
> +static void __lmce_enable(void)
> +{
> +	u64 val;
> +
> +	rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
> +	val |= MCG_EXT_CTL_LMCE_EN;
> +	wrmsrl(MSR_IA32_MCG_EXT_CTL, val);
> +}

Called only in intel_init_lmce(), merge it into it.

> +
> +
> +void intel_init_lmce(void)
> +{
> +	if (!lmce_supported())
> +		return;
> +
> +	__lmce_enable();
> +}
> +
> +void lmce_enable(void)

This one's unused, drop it.

> +{
> +	intel_init_lmce();
> +}
> +
> +void lmce_disable(void)
> +{
> +	u64 val;
> +
> +	rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
> +	val &= ~MCG_EXT_CTL_LMCE_EN;
> +	wrmsrl(MSR_IA32_MCG_EXT_CTL, val);
> +}

Called only in lmce_clear(), merge it into it.

> +
> +/*
> + * Disable LMCE on this CPU for all banks it owns when it goes down.
> + * This allows other CPUs to claim the banks on rediscovery.
> + */
> +void lmce_clear(void)
> +{
> +	if (!lmce_supported())
> +		return;
> +	lmce_disable();
> +}
> +
>  void mce_intel_feature_init(struct cpuinfo_x86 *c)
>  {
>  	intel_init_thermal(c);
> -- 
> 1.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-edac" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--