From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Vinod Koul <vinod.koul@intel.com>,
dmaengine@vger.kernel.org,
Nicolas Ferre <nicolas.ferre@atmel.com>,
Alexandre Belloni <alexandre.belloni@free-electrons.com>,
Thomas Petazzoni <thomas@free-electrons.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/2] dmaengine: hdmac: Implement interleaved transfers
Date: Tue, 2 Jun 2015 11:19:51 +0200 [thread overview]
Message-ID: <20150602091951.GV23777@lukather> (raw)
In-Reply-To: <20150601083216.GH25118@odux.rfo.atmel.com>
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Hi,
On Mon, Jun 01, 2015 at 10:32:16AM +0200, Ludovic Desroches wrote:
> > channel_writel(atchan, CTRLA, 0);
> > channel_writel(atchan, CTRLB, 0);
> > channel_writel(atchan, DSCR, first->txd.phys);
> > + channel_writel(atchan, SPIP, ATC_SPIP_HOLE(first->src_hole) |
> > + ATC_SPIP_BOUNDARY(first->boundary));
> > + channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) |
> > + ATC_DPIP_BOUNDARY(first->boundary));
>
> Can't we get a trivial condition to perform these two writes only if
> needed?
Is that really needed?
My understanding is that the hardware will only take this into account
if we set the ATC_SRC_PIP and ATC_DST_PIP bits anyway, so the check is
already there.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2015-06-02 9:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-27 14:01 [PATCH 0/2] dmaengine: hdmac: Implement interleaved transfers support Maxime Ripard
2015-05-27 14:01 ` [PATCH 1/2] dmaengine: Move icg helpers to global header Maxime Ripard
2015-06-01 8:14 ` Ludovic Desroches
2015-05-27 14:01 ` [PATCH 2/2] dmaengine: hdmac: Implement interleaved transfers Maxime Ripard
2015-06-01 8:32 ` Ludovic Desroches
2015-06-02 9:19 ` Maxime Ripard [this message]
2015-06-12 12:44 ` [PATCH 0/2] dmaengine: hdmac: Implement interleaved transfers support Vinod Koul
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