From: Dan Carpenter <dan.carpenter@oracle.com>
To: David Decotigny <ddecotig@gmail.com>
Cc: Oleg Drokin <oleg.drokin@intel.com>,
Andreas Dilger <andreas.dilger@intel.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
HPDD-discuss@ml01.01.org, devel@driverdev.osuosl.org,
linux-kernel@vger.kernel.org, Liang Zhen <liang.zhen@intel.com>,
Peng Tao <bergwolf@gmail.com>,
Doug Oucharek <doug.s.oucharek@intel.com>,
Amir Shehata <amir.shehata@intel.com>,
Isaac Huang <he.huang@intel.com>
Subject: Re: [PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion
Date: Sun, 7 Jun 2015 15:09:22 +0300 [thread overview]
Message-ID: <20150607120922.GU28762@mwanda> (raw)
In-Reply-To: <1433637240-24223-3-git-send-email-ddecotig@gmail.com>
On Sat, Jun 06, 2015 at 05:34:00PM -0700, David Decotigny wrote:
> Source and destination have the same little-endian annotation: this
> patch removes forced conversion from host byte order to little-endian.
The patch seems correct but the changelog is a bit wrong. It will
change it from little endian to host endian but we don't want the dest
to be host endian, we want it to be little endain.
regards,
dan carpenter
next prev parent reply other threads:[~2015-06-07 12:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-07 0:33 [PATCH v2 0/2] staging: rtl8723au: core: endianness issues David Decotigny
2015-06-07 0:33 ` [PATCH v2 1/2] staging: rtl8723au: core: avoid bitwise arithmetic with forced endianness David Decotigny
2015-06-07 11:20 ` Dan Carpenter
2015-06-08 0:33 ` David Decotigny
2015-06-07 0:34 ` [PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion David Decotigny
2015-06-07 12:09 ` Dan Carpenter [this message]
-- strict thread matches above, loose matches on Subject: below --
2015-06-08 0:43 [PATCH v2 0/2] staging: rtl8723au: core: endianness issues David Decotigny
2015-06-08 0:43 ` [PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion David Decotigny
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