From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932345AbbFHUDV (ORCPT ); Mon, 8 Jun 2015 16:03:21 -0400 Received: from mail-wi0-f178.google.com ([209.85.212.178]:38422 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752584AbbFHUDN (ORCPT ); Mon, 8 Jun 2015 16:03:13 -0400 Date: Mon, 8 Jun 2015 22:03:08 +0200 From: Ingo Molnar To: Dave Hansen Cc: Mel Gorman , Andrew Morton , Rik van Riel , Hugh Dickins , Minchan Kim , Andi Kleen , H Peter Anvin , Linux-MM , LKML , Linus Torvalds , Peter Zijlstra , Thomas Gleixner Subject: Re: [PATCH 0/3] TLB flush multiple pages per IPI v5 Message-ID: <20150608200308.GA16978@gmail.com> References: <1433767854-24408-1-git-send-email-mgorman@suse.de> <20150608174551.GA27558@gmail.com> <5575DD33.3000400@intel.com> <20150608195237.GA15429@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150608195237.GA15429@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Ingo Molnar wrote: > So what I measured agrees generally with the comment you added in the commit: > > + * Each single flush is about 100 ns, so this caps the maximum overhead at > + * _about_ 3,000 ns. > > Let that sink through: 3,000 nsecs = 3 usecs, that's like eternity! > > A CR3 driven TLB flush takes less time than a single INVLPG (!): > > [ 0.389028] x86/fpu: Cost of: __flush_tlb() fn : 96 cycles > [ 0.405885] x86/fpu: Cost of: __flush_tlb_one() fn : 260 cycles > [ 0.414302] x86/fpu: Cost of: __flush_tlb_range() fn : 404 cycles > > it's true that a full flush has hidden costs not measured above, because it has > knock-on effects (because it drops non-global TLB entries), but it's not _that_ > bad due to: > > - there almost always being a L1 or L2 cache miss when a TLB miss occurs, > which latency can be overlaid > > - global bit being held for kernel entries > > - user-space with high memory pressure trashing through TLBs typically I also have cache-cold numbers from another (Intel) system: [ 0.176473] x86/bench:########################################################################## [ 0.185656] x86/bench: Running x86 benchmarks: cache- hot / cold cycles [ 1.234448] x86/bench: Cost of: null : 35 / 73 cycles [ ........] [ 27.930451] x86/bench:######## MM instructions: ###################################### [ 28.979251] x86/bench: Cost of: __flush_tlb() fn : 251 / 366 cycles [ 30.028795] x86/bench: Cost of: __flush_tlb_global() fn : 746 / 1795 cycles [ 31.077862] x86/bench: Cost of: __flush_tlb_one() fn : 237 / 883 cycles [ 32.127371] x86/bench: Cost of: __flush_tlb_range() fn : 312 / 1603 cycles [ 35.254202] x86/bench: Cost of: wbinvd() insn : 2491761 / 2491922 cycles Note how the numbers are even worse in the cache-cold case: the algorithmic complexity of __flush_tlb_range() versus __flush_tlb() makes it run slower (because we miss the I$), while the TLB cache-preservation argument is probably weaker, because when we are cache cold then TLB refill latency probably matters less (as it can be overlapped). So __flush_tlb_range() is software trying to beat hardware, and that's almost always a bad idea on x86. Thanks, Ingo