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* Updated Haswell uncore PMU patchkit
@ 2015-06-18 20:45 Andi Kleen
  2015-06-18 20:46 ` [PATCH 1/3] x86, perf, uncore: Add support for ARB uncore PMU on Sandy/IvyBridge Andi Kleen
                   ` (2 more replies)
  0 siblings, 3 replies; 10+ messages in thread
From: Andi Kleen @ 2015-06-18 20:45 UTC (permalink / raw)
  To: peterz; +Cc: linux-kernel

This version avoids registering the CPU notifier if nothing
is detected.
-Andi


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Another Haswell uncore patchkit
@ 2015-06-18 23:02 Andi Kleen
  2015-06-18 23:02 ` [PATCH 3/3] x86, perf, uncore: Don't make MSR uncore depend on PCI uncore Andi Kleen
  0 siblings, 1 reply; 10+ messages in thread
From: Andi Kleen @ 2015-06-18 23:02 UTC (permalink / raw)
  To: peterz; +Cc: linux-kernel, tglx

This version returns an error if probing both types of uncores fails.


^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 1/3] x86, perf, uncore: Add support for ARB uncore PMU on Sandy/IvyBridge
@ 2015-06-15  5:57 Andi Kleen
  2015-06-15  5:57 ` [PATCH 3/3] x86, perf, uncore: Don't make MSR uncore depend on PCI uncore Andi Kleen
  0 siblings, 1 reply; 10+ messages in thread
From: Andi Kleen @ 2015-06-15  5:57 UTC (permalink / raw)
  To: peterz; +Cc: eranian, linux-kernel, kan.liang, Andi Kleen

From: Andi Kleen <ak@linux.intel.com>

Add a new "ARB" uncore PMU that is used to monitor the uncore queue
arbiter. This is useful to measure uncore queue occupancy and similar
statistics. The registers all have the same format as the
existing CBOX PMU.

Also move the event constraints from the CBOX to ARB. The 0x80+
events are ARB events and cannot be scheduled on a CBOX PMU.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
index 4562e9e..3eff721 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
@@ -44,6 +44,11 @@
 #define SNB_UNC_CBO_0_PER_CTR0                  0x706
 #define SNB_UNC_CBO_MSR_OFFSET                  0x10
 
+/* SNB ARB register */
+#define SNB_UNC_ARB_PER_CTR0			0x3b0
+#define SNB_UNC_ARB_PERFEVTSEL0			0x3b2
+#define SNB_UNC_ARB_MSR_OFFSET			0x10
+
 /* NHM global control register */
 #define NHM_UNC_PERF_GLOBAL_CTL                 0x391
 #define NHM_UNC_FIXED_CTR                       0x394
@@ -114,7 +119,7 @@ static struct intel_uncore_ops snb_uncore_msr_ops = {
 	.read_counter	= uncore_msr_read_counter,
 };
 
-static struct event_constraint snb_uncore_cbox_constraints[] = {
+static struct event_constraint snb_uncore_arb_constraints[] = {
 	UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
 	UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
 	EVENT_CONSTRAINT_END
@@ -133,14 +138,28 @@ static struct intel_uncore_type snb_uncore_cbox = {
 	.single_fixed	= 1,
 	.event_mask	= SNB_UNC_RAW_EVENT_MASK,
 	.msr_offset	= SNB_UNC_CBO_MSR_OFFSET,
-	.constraints	= snb_uncore_cbox_constraints,
 	.ops		= &snb_uncore_msr_ops,
 	.format_group	= &snb_uncore_format_group,
 	.event_descs	= snb_uncore_events,
 };
 
+static struct intel_uncore_type snb_uncore_arb = {
+	.name		= "arb",
+	.num_counters   = 2,
+	.num_boxes	= 1,
+	.perf_ctr_bits	= 44,
+	.perf_ctr	= SNB_UNC_ARB_PER_CTR0,
+	.event_ctl	= SNB_UNC_ARB_PERFEVTSEL0,
+	.event_mask	= SNB_UNC_RAW_EVENT_MASK,
+	.msr_offset	= SNB_UNC_ARB_MSR_OFFSET,
+	.constraints	= snb_uncore_arb_constraints,
+	.ops		= &snb_uncore_msr_ops,
+	.format_group	= &snb_uncore_format_group,
+};
+
 static struct intel_uncore_type *snb_msr_uncores[] = {
 	&snb_uncore_cbox,
+	&snb_uncore_arb,
 	NULL,
 };
 
-- 
2.4.2


^ permalink raw reply related	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2015-06-18 23:02 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-06-18 20:45 Updated Haswell uncore PMU patchkit Andi Kleen
2015-06-18 20:46 ` [PATCH 1/3] x86, perf, uncore: Add support for ARB uncore PMU on Sandy/IvyBridge Andi Kleen
2015-06-18 20:46 ` [PATCH 2/3] x86, perf, uncore: Use Sandy Bridge client PMU on Haswell/Broadwell Andi Kleen
2015-06-18 20:46 ` [PATCH 3/3] x86, perf, uncore: Don't make MSR uncore depend on PCI uncore Andi Kleen
2015-06-18 21:12   ` Thomas Gleixner
2015-06-18 22:48     ` Andi Kleen
2015-06-18 22:57       ` Thomas Gleixner
  -- strict thread matches above, loose matches on Subject: below --
2015-06-18 23:02 Another Haswell uncore patchkit Andi Kleen
2015-06-18 23:02 ` [PATCH 3/3] x86, perf, uncore: Don't make MSR uncore depend on PCI uncore Andi Kleen
2015-06-15  5:57 [PATCH 1/3] x86, perf, uncore: Add support for ARB uncore PMU on Sandy/IvyBridge Andi Kleen
2015-06-15  5:57 ` [PATCH 3/3] x86, perf, uncore: Don't make MSR uncore depend on PCI uncore Andi Kleen
2015-06-16 12:06   ` Thomas Gleixner

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