From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755541AbbGFPof (ORCPT ); Mon, 6 Jul 2015 11:44:35 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:36916 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752798AbbGFPoa (ORCPT ); Mon, 6 Jul 2015 11:44:30 -0400 Date: Mon, 6 Jul 2015 17:44:25 +0200 From: Ingo Molnar To: Andy Shevchenko Cc: x86@kernel.org, Aubrey Li , "Rafael J . Wysocki" , "Kumar P, Mahesh" , linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Subject: Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface Message-ID: <20150706154425.GA19665@gmail.com> References: <1436192944-56496-1-git-send-email-andriy.shevchenko@linux.intel.com> <1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Andy Shevchenko wrote: > The patch adds CHT PMC interface. This exposes all the South IP device power > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are > not aligned. This is fixed by splitting a common mapping on per register basis. > > Signed-off-by: Kumar P Mahesh > Signed-off-by: Andy Shevchenko That's a weird signoff sequence. I changed it to: Signed-off-by: Andy Shevchenko Acked-by: Kumar P Mahesh Thanks, Ingo