Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface

[Ingo Molnar <mingo@kernel.org>]

* Thomas Gleixner <tglx@linutronix.de> wrote:

> On Mon, 6 Jul 2015, Ingo Molnar wrote:
>  
> > * Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> > 
> > > The patch adds CHT PMC interface. This exposes all the South IP device power
> > > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> > > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> > > not aligned. This is fixed by splitting a common mapping on per register basis.
> > > 
> > > Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > 
> > That's a weird signoff sequence. I changed it to:
> > 
> >  Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >  Acked-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> 
> It might lack a From: Kumar ... 

Yeah, and got lost due to a rebase. Will change it to that, to preserve 
authorship. Won't push it out before I hear back from Andy though.

Thanks,

	Ingo