* [PATCH v3 1/5] x86: pmc_atom: export accessors to PMC registers
2015-07-06 14:28 [PATCH v3 0/5] x86: pmc_atom: Add Cherrytrail support Andy Shevchenko
@ 2015-07-06 14:29 ` Andy Shevchenko
2015-07-06 16:34 ` [tip:x86/platform] x86/platform/intel/pmc_atom: Export " tip-bot for Andy Shevchenko
2015-07-06 14:29 ` [PATCH v3 2/5] x86: pmc_atom: print index of device in loop Andy Shevchenko
` (3 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Andy Shevchenko @ 2015-07-06 14:29 UTC (permalink / raw)
To: x86, Aubrey Li, Rafael J . Wysocki, Kumar P, Mahesh, linux-kernel,
linux-acpi, Ingo Molnar
Cc: Andy Shevchenko
Export pmc_atom_read() and pmc_atom_write() accessors to the PMC registers. On
early initcall stages the functions will return -ENODEV, and caller has to wait
when it will be available. Additionally make absence of debugfs a non-fatal
error.
The patch will be useful for the upcoming fixes regarding to LPSS block found
on Intel BayTrail-T and Braswell.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/include/asm/pmc_atom.h | 4 ++++
arch/x86/kernel/pmc_atom.c | 49 ++++++++++++++++++++++++++++-------------
2 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
index bc0fc08..6ee2200 100644
--- a/arch/x86/include/asm/pmc_atom.h
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -126,4 +126,8 @@
#define SLEEP_TYPE_MASK 0xFFFFECFF
#define SLEEP_TYPE_S5 0x1C00
#define SLEEP_ENABLE 0x2000
+
+extern int pmc_atom_read(int offset, u32 *value);
+extern int pmc_atom_write(int offset, u32 value);
+
#endif /* PMC_ATOM_H */
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index d66a4fe..4e1242e 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -31,6 +31,7 @@ struct pmc_dev {
#ifdef CONFIG_DEBUG_FS
struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
+ bool init;
};
static struct pmc_dev pmc_device;
@@ -111,6 +112,30 @@ static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
writel(val, pmc->regmap + reg_offset);
}
+int pmc_atom_read(int offset, u32 *value)
+{
+ struct pmc_dev *pmc = &pmc_device;
+
+ if (!pmc->init)
+ return -ENODEV;
+
+ *value = pmc_reg_read(pmc, offset);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pmc_atom_read);
+
+int pmc_atom_write(int offset, u32 value)
+{
+ struct pmc_dev *pmc = &pmc_device;
+
+ if (!pmc->init)
+ return -ENODEV;
+
+ pmc_reg_write(pmc, offset, value);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pmc_atom_write);
+
static void pmc_power_off(void)
{
u16 pm1_cnt_port;
@@ -250,7 +275,7 @@ static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
debugfs_remove_recursive(pmc->dbgfs_dir);
}
-static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
+static int pmc_dbgfs_register(struct pmc_dev *pmc)
{
struct dentry *dir, *f;
@@ -262,24 +287,18 @@ static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_dev_state_ops);
- if (!f) {
- dev_err(&pdev->dev, "dev_state register failed\n");
+ if (!f)
goto err;
- }
f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_pss_state_ops);
- if (!f) {
- dev_err(&pdev->dev, "pss_state register failed\n");
+ if (!f)
goto err;
- }
f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_sleep_tmr_ops);
- if (!f) {
- dev_err(&pdev->dev, "sleep_state register failed\n");
+ if (!f)
goto err;
- }
return 0;
err:
@@ -287,7 +306,7 @@ err:
return -ENODEV;
}
#else
-static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
+static int pmc_dbgfs_register(struct pmc_dev *pmc)
{
return 0;
}
@@ -318,11 +337,11 @@ static int pmc_setup_dev(struct pci_dev *pdev)
/* PMC hardware registers setup */
pmc_hw_reg_setup(pmc);
- ret = pmc_dbgfs_register(pmc, pdev);
- if (ret) {
- iounmap(pmc->regmap);
- }
+ ret = pmc_dbgfs_register(pmc);
+ if (ret)
+ dev_warn(&pdev->dev, "debugfs register failed\n");
+ pmc->init = true;
return ret;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [tip:x86/platform] x86/platform/intel/pmc_atom: Export accessors to PMC registers
2015-07-06 14:29 ` [PATCH v3 1/5] x86: pmc_atom: export accessors to PMC registers Andy Shevchenko
@ 2015-07-06 16:34 ` tip-bot for Andy Shevchenko
0 siblings, 0 replies; 20+ messages in thread
From: tip-bot for Andy Shevchenko @ 2015-07-06 16:34 UTC (permalink / raw)
To: linux-tip-commits
Cc: mahesh.kumar.p, torvalds, linux-kernel, hpa, rafael.j.wysocki,
andriy.shevchenko, tglx, mingo, aubrey.li, peterz
Commit-ID: 68872eb9b19bbd85883262a4e0927b487653816c
Gitweb: http://git.kernel.org/tip/68872eb9b19bbd85883262a4e0927b487653816c
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Mon, 6 Jul 2015 17:29:00 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 6 Jul 2015 17:42:45 +0200
x86/platform/intel/pmc_atom: Export accessors to PMC registers
Export the pmc_atom_read() and pmc_atom_write() accessors to the PMC
registers. On early initcall stages the functions will return
-ENODEV, and caller has to wait when it will be available.
Additionally make absence of debugfs a non-fatal error.
The patch will be useful for the upcoming fixes regarding to the
LPSS block found on Intel BayTrail-T and Braswell.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1436192944-56496-2-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/pmc_atom.h | 4 ++++
arch/x86/kernel/pmc_atom.c | 49 ++++++++++++++++++++++++++++-------------
2 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
index bc0fc08..6ee2200 100644
--- a/arch/x86/include/asm/pmc_atom.h
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -126,4 +126,8 @@
#define SLEEP_TYPE_MASK 0xFFFFECFF
#define SLEEP_TYPE_S5 0x1C00
#define SLEEP_ENABLE 0x2000
+
+extern int pmc_atom_read(int offset, u32 *value);
+extern int pmc_atom_write(int offset, u32 value);
+
#endif /* PMC_ATOM_H */
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index d66a4fe..4e1242e 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -31,6 +31,7 @@ struct pmc_dev {
#ifdef CONFIG_DEBUG_FS
struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
+ bool init;
};
static struct pmc_dev pmc_device;
@@ -111,6 +112,30 @@ static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
writel(val, pmc->regmap + reg_offset);
}
+int pmc_atom_read(int offset, u32 *value)
+{
+ struct pmc_dev *pmc = &pmc_device;
+
+ if (!pmc->init)
+ return -ENODEV;
+
+ *value = pmc_reg_read(pmc, offset);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pmc_atom_read);
+
+int pmc_atom_write(int offset, u32 value)
+{
+ struct pmc_dev *pmc = &pmc_device;
+
+ if (!pmc->init)
+ return -ENODEV;
+
+ pmc_reg_write(pmc, offset, value);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pmc_atom_write);
+
static void pmc_power_off(void)
{
u16 pm1_cnt_port;
@@ -250,7 +275,7 @@ static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
debugfs_remove_recursive(pmc->dbgfs_dir);
}
-static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
+static int pmc_dbgfs_register(struct pmc_dev *pmc)
{
struct dentry *dir, *f;
@@ -262,24 +287,18 @@ static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_dev_state_ops);
- if (!f) {
- dev_err(&pdev->dev, "dev_state register failed\n");
+ if (!f)
goto err;
- }
f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_pss_state_ops);
- if (!f) {
- dev_err(&pdev->dev, "pss_state register failed\n");
+ if (!f)
goto err;
- }
f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_sleep_tmr_ops);
- if (!f) {
- dev_err(&pdev->dev, "sleep_state register failed\n");
+ if (!f)
goto err;
- }
return 0;
err:
@@ -287,7 +306,7 @@ err:
return -ENODEV;
}
#else
-static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
+static int pmc_dbgfs_register(struct pmc_dev *pmc)
{
return 0;
}
@@ -318,11 +337,11 @@ static int pmc_setup_dev(struct pci_dev *pdev)
/* PMC hardware registers setup */
pmc_hw_reg_setup(pmc);
- ret = pmc_dbgfs_register(pmc, pdev);
- if (ret) {
- iounmap(pmc->regmap);
- }
+ ret = pmc_dbgfs_register(pmc);
+ if (ret)
+ dev_warn(&pdev->dev, "debugfs register failed\n");
+ pmc->init = true;
return ret;
}
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 2/5] x86: pmc_atom: print index of device in loop
2015-07-06 14:28 [PATCH v3 0/5] x86: pmc_atom: Add Cherrytrail support Andy Shevchenko
2015-07-06 14:29 ` [PATCH v3 1/5] x86: pmc_atom: export accessors to PMC registers Andy Shevchenko
@ 2015-07-06 14:29 ` Andy Shevchenko
2015-07-06 16:34 ` [tip:x86/platform] x86/platform/intel/pmc_atom: Print " tip-bot for Andy Shevchenko
2015-07-06 14:29 ` [PATCH v3 3/5] x86: pmc_atom: supply register mappings via pmc object Andy Shevchenko
` (2 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Andy Shevchenko @ 2015-07-06 14:29 UTC (permalink / raw)
To: x86, Aubrey Li, Rafael J . Wysocki, Kumar P, Mahesh, linux-kernel,
linux-acpi, Ingo Molnar
Cc: Andy Shevchenko
The register mapping may change from one platform to another. Thus, indices
might be not the same on different platforms. The patch makes the code to print
the device index dynamically at run time.
The patch also changes the for loop to iterate over the map until a terminator
is found.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/kernel/pmc_atom.c | 126 ++++++++++++++++++++++-----------------------
1 file changed, 63 insertions(+), 63 deletions(-)
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index 4e1242e..c7dca07 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -43,63 +43,65 @@ struct pmc_bit_map {
};
static const struct pmc_bit_map dev_map[] = {
- {"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
- {"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
- {"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
- {"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
- {"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
- {"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
- {"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
- {"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
- {"8 - SCC_EMMC", BIT_SCC_EMMC},
- {"9 - SCC_SDIO", BIT_SCC_SDIO},
- {"10 - SCC_SDCARD", BIT_SCC_SDCARD},
- {"11 - SCC_MIPI", BIT_SCC_MIPI},
- {"12 - HDA", BIT_HDA},
- {"13 - LPE", BIT_LPE},
- {"14 - OTG", BIT_OTG},
- {"15 - USH", BIT_USH},
- {"16 - GBE", BIT_GBE},
- {"17 - SATA", BIT_SATA},
- {"18 - USB_EHCI", BIT_USB_EHCI},
- {"19 - SEC", BIT_SEC},
- {"20 - PCIE_PORT0", BIT_PCIE_PORT0},
- {"21 - PCIE_PORT1", BIT_PCIE_PORT1},
- {"22 - PCIE_PORT2", BIT_PCIE_PORT2},
- {"23 - PCIE_PORT3", BIT_PCIE_PORT3},
- {"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
- {"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
- {"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
- {"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
- {"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
- {"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
- {"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
- {"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
- {"32 - SMB", BIT_SMB},
- {"33 - OTG_SS_PHY", BIT_OTG_SS_PHY},
- {"34 - USH_SS_PHY", BIT_USH_SS_PHY},
- {"35 - DFX", BIT_DFX},
+ {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
+ {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
+ {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
+ {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
+ {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
+ {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
+ {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
+ {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
+ {"SCC_EMMC", BIT_SCC_EMMC},
+ {"SCC_SDIO", BIT_SCC_SDIO},
+ {"SCC_SDCARD", BIT_SCC_SDCARD},
+ {"SCC_MIPI", BIT_SCC_MIPI},
+ {"HDA", BIT_HDA},
+ {"LPE", BIT_LPE},
+ {"OTG", BIT_OTG},
+ {"USH", BIT_USH},
+ {"GBE", BIT_GBE},
+ {"SATA", BIT_SATA},
+ {"USB_EHCI", BIT_USB_EHCI},
+ {"SEC", BIT_SEC},
+ {"PCIE_PORT0", BIT_PCIE_PORT0},
+ {"PCIE_PORT1", BIT_PCIE_PORT1},
+ {"PCIE_PORT2", BIT_PCIE_PORT2},
+ {"PCIE_PORT3", BIT_PCIE_PORT3},
+ {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
+ {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
+ {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
+ {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
+ {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
+ {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
+ {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
+ {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
+ {"SMB", BIT_SMB},
+ {"OTG_SS_PHY", BIT_OTG_SS_PHY},
+ {"USH_SS_PHY", BIT_USH_SS_PHY},
+ {"DFX", BIT_DFX},
+ {},
};
static const struct pmc_bit_map pss_map[] = {
- {"0 - GBE", PMC_PSS_BIT_GBE},
- {"1 - SATA", PMC_PSS_BIT_SATA},
- {"2 - HDA", PMC_PSS_BIT_HDA},
- {"3 - SEC", PMC_PSS_BIT_SEC},
- {"4 - PCIE", PMC_PSS_BIT_PCIE},
- {"5 - LPSS", PMC_PSS_BIT_LPSS},
- {"6 - LPE", PMC_PSS_BIT_LPE},
- {"7 - DFX", PMC_PSS_BIT_DFX},
- {"8 - USH_CTRL", PMC_PSS_BIT_USH_CTRL},
- {"9 - USH_SUS", PMC_PSS_BIT_USH_SUS},
- {"10 - USH_VCCS", PMC_PSS_BIT_USH_VCCS},
- {"11 - USH_VCCA", PMC_PSS_BIT_USH_VCCA},
- {"12 - OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
- {"13 - OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
- {"14 - OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
- {"15 - OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
- {"16 - USB", PMC_PSS_BIT_USB},
- {"17 - USB_SUS", PMC_PSS_BIT_USB_SUS},
+ {"GBE", PMC_PSS_BIT_GBE},
+ {"SATA", PMC_PSS_BIT_SATA},
+ {"HDA", PMC_PSS_BIT_HDA},
+ {"SEC", PMC_PSS_BIT_SEC},
+ {"PCIE", PMC_PSS_BIT_PCIE},
+ {"LPSS", PMC_PSS_BIT_LPSS},
+ {"LPE", PMC_PSS_BIT_LPE},
+ {"DFX", PMC_PSS_BIT_DFX},
+ {"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
+ {"USH_SUS", PMC_PSS_BIT_USH_SUS},
+ {"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
+ {"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
+ {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
+ {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
+ {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
+ {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
+ {"USB", PMC_PSS_BIT_USB},
+ {"USB_SUS", PMC_PSS_BIT_USB_SUS},
+ {},
};
static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
@@ -172,16 +174,14 @@ static int pmc_dev_state_show(struct seq_file *s, void *unused)
struct pmc_dev *pmc = s->private;
u32 func_dis, func_dis_2, func_dis_index;
u32 d3_sts_0, d3_sts_1, d3_sts_index;
- int dev_num, dev_index, reg_index;
+ int dev_index, reg_index;
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
- dev_num = ARRAY_SIZE(dev_map);
-
- for (dev_index = 0; dev_index < dev_num; dev_index++) {
+ for (dev_index = 0; dev_map[dev_index].name; dev_index++) {
reg_index = dev_index / PMC_REG_BIT_WIDTH;
if (reg_index) {
func_dis_index = func_dis_2;
@@ -191,8 +191,8 @@ static int pmc_dev_state_show(struct seq_file *s, void *unused)
d3_sts_index = d3_sts_0;
}
- seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
- dev_map[dev_index].name,
+ seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
+ dev_index, dev_map[dev_index].name,
dev_map[dev_index].bit_mask & func_dis_index ?
"Disabled" : "Enabled ",
dev_map[dev_index].bit_mask & d3_sts_index ?
@@ -219,9 +219,9 @@ static int pmc_pss_state_show(struct seq_file *s, void *unused)
u32 pss = pmc_reg_read(pmc, PMC_PSS);
int pss_index;
- for (pss_index = 0; pss_index < ARRAY_SIZE(pss_map); pss_index++) {
- seq_printf(s, "Island: %-32s\tState: %s\n",
- pss_map[pss_index].name,
+ for (pss_index = 0; pss_map[pss_index].name; pss_index++) {
+ seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
+ pss_index, pss_map[pss_index].name,
pss_map[pss_index].bit_mask & pss ? "Off" : "On");
}
return 0;
--
2.1.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [tip:x86/platform] x86/platform/intel/pmc_atom: Print index of device in loop
2015-07-06 14:29 ` [PATCH v3 2/5] x86: pmc_atom: print index of device in loop Andy Shevchenko
@ 2015-07-06 16:34 ` tip-bot for Andy Shevchenko
0 siblings, 0 replies; 20+ messages in thread
From: tip-bot for Andy Shevchenko @ 2015-07-06 16:34 UTC (permalink / raw)
To: linux-tip-commits
Cc: andriy.shevchenko, tglx, mahesh.kumar.p, aubrey.li, linux-kernel,
mingo, hpa, rafael.j.wysocki
Commit-ID: c3c65aa6d43f9e9f23f688848b08ffec97be893b
Gitweb: http://git.kernel.org/tip/c3c65aa6d43f9e9f23f688848b08ffec97be893b
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Mon, 6 Jul 2015 17:29:01 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 6 Jul 2015 17:42:46 +0200
x86/platform/intel/pmc_atom: Print index of device in loop
The register mapping may change from one platform to another.
Thus, indices might be not the same on different platforms. The
patch makes the code to print the device index dynamically at
run time.
The patch also changes the for loop to iterate over the map
until a terminator is found.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Link: http://lkml.kernel.org/r/1436192944-56496-3-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/pmc_atom.c | 126 ++++++++++++++++++++++-----------------------
1 file changed, 63 insertions(+), 63 deletions(-)
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index 4e1242e..c7dca07 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -43,63 +43,65 @@ struct pmc_bit_map {
};
static const struct pmc_bit_map dev_map[] = {
- {"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
- {"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
- {"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
- {"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
- {"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
- {"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
- {"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
- {"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
- {"8 - SCC_EMMC", BIT_SCC_EMMC},
- {"9 - SCC_SDIO", BIT_SCC_SDIO},
- {"10 - SCC_SDCARD", BIT_SCC_SDCARD},
- {"11 - SCC_MIPI", BIT_SCC_MIPI},
- {"12 - HDA", BIT_HDA},
- {"13 - LPE", BIT_LPE},
- {"14 - OTG", BIT_OTG},
- {"15 - USH", BIT_USH},
- {"16 - GBE", BIT_GBE},
- {"17 - SATA", BIT_SATA},
- {"18 - USB_EHCI", BIT_USB_EHCI},
- {"19 - SEC", BIT_SEC},
- {"20 - PCIE_PORT0", BIT_PCIE_PORT0},
- {"21 - PCIE_PORT1", BIT_PCIE_PORT1},
- {"22 - PCIE_PORT2", BIT_PCIE_PORT2},
- {"23 - PCIE_PORT3", BIT_PCIE_PORT3},
- {"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
- {"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
- {"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
- {"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
- {"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
- {"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
- {"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
- {"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
- {"32 - SMB", BIT_SMB},
- {"33 - OTG_SS_PHY", BIT_OTG_SS_PHY},
- {"34 - USH_SS_PHY", BIT_USH_SS_PHY},
- {"35 - DFX", BIT_DFX},
+ {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
+ {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
+ {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
+ {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
+ {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
+ {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
+ {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
+ {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
+ {"SCC_EMMC", BIT_SCC_EMMC},
+ {"SCC_SDIO", BIT_SCC_SDIO},
+ {"SCC_SDCARD", BIT_SCC_SDCARD},
+ {"SCC_MIPI", BIT_SCC_MIPI},
+ {"HDA", BIT_HDA},
+ {"LPE", BIT_LPE},
+ {"OTG", BIT_OTG},
+ {"USH", BIT_USH},
+ {"GBE", BIT_GBE},
+ {"SATA", BIT_SATA},
+ {"USB_EHCI", BIT_USB_EHCI},
+ {"SEC", BIT_SEC},
+ {"PCIE_PORT0", BIT_PCIE_PORT0},
+ {"PCIE_PORT1", BIT_PCIE_PORT1},
+ {"PCIE_PORT2", BIT_PCIE_PORT2},
+ {"PCIE_PORT3", BIT_PCIE_PORT3},
+ {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
+ {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
+ {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
+ {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
+ {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
+ {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
+ {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
+ {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
+ {"SMB", BIT_SMB},
+ {"OTG_SS_PHY", BIT_OTG_SS_PHY},
+ {"USH_SS_PHY", BIT_USH_SS_PHY},
+ {"DFX", BIT_DFX},
+ {},
};
static const struct pmc_bit_map pss_map[] = {
- {"0 - GBE", PMC_PSS_BIT_GBE},
- {"1 - SATA", PMC_PSS_BIT_SATA},
- {"2 - HDA", PMC_PSS_BIT_HDA},
- {"3 - SEC", PMC_PSS_BIT_SEC},
- {"4 - PCIE", PMC_PSS_BIT_PCIE},
- {"5 - LPSS", PMC_PSS_BIT_LPSS},
- {"6 - LPE", PMC_PSS_BIT_LPE},
- {"7 - DFX", PMC_PSS_BIT_DFX},
- {"8 - USH_CTRL", PMC_PSS_BIT_USH_CTRL},
- {"9 - USH_SUS", PMC_PSS_BIT_USH_SUS},
- {"10 - USH_VCCS", PMC_PSS_BIT_USH_VCCS},
- {"11 - USH_VCCA", PMC_PSS_BIT_USH_VCCA},
- {"12 - OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
- {"13 - OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
- {"14 - OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
- {"15 - OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
- {"16 - USB", PMC_PSS_BIT_USB},
- {"17 - USB_SUS", PMC_PSS_BIT_USB_SUS},
+ {"GBE", PMC_PSS_BIT_GBE},
+ {"SATA", PMC_PSS_BIT_SATA},
+ {"HDA", PMC_PSS_BIT_HDA},
+ {"SEC", PMC_PSS_BIT_SEC},
+ {"PCIE", PMC_PSS_BIT_PCIE},
+ {"LPSS", PMC_PSS_BIT_LPSS},
+ {"LPE", PMC_PSS_BIT_LPE},
+ {"DFX", PMC_PSS_BIT_DFX},
+ {"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
+ {"USH_SUS", PMC_PSS_BIT_USH_SUS},
+ {"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
+ {"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
+ {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
+ {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
+ {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
+ {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
+ {"USB", PMC_PSS_BIT_USB},
+ {"USB_SUS", PMC_PSS_BIT_USB_SUS},
+ {},
};
static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
@@ -172,16 +174,14 @@ static int pmc_dev_state_show(struct seq_file *s, void *unused)
struct pmc_dev *pmc = s->private;
u32 func_dis, func_dis_2, func_dis_index;
u32 d3_sts_0, d3_sts_1, d3_sts_index;
- int dev_num, dev_index, reg_index;
+ int dev_index, reg_index;
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
- dev_num = ARRAY_SIZE(dev_map);
-
- for (dev_index = 0; dev_index < dev_num; dev_index++) {
+ for (dev_index = 0; dev_map[dev_index].name; dev_index++) {
reg_index = dev_index / PMC_REG_BIT_WIDTH;
if (reg_index) {
func_dis_index = func_dis_2;
@@ -191,8 +191,8 @@ static int pmc_dev_state_show(struct seq_file *s, void *unused)
d3_sts_index = d3_sts_0;
}
- seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
- dev_map[dev_index].name,
+ seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
+ dev_index, dev_map[dev_index].name,
dev_map[dev_index].bit_mask & func_dis_index ?
"Disabled" : "Enabled ",
dev_map[dev_index].bit_mask & d3_sts_index ?
@@ -219,9 +219,9 @@ static int pmc_pss_state_show(struct seq_file *s, void *unused)
u32 pss = pmc_reg_read(pmc, PMC_PSS);
int pss_index;
- for (pss_index = 0; pss_index < ARRAY_SIZE(pss_map); pss_index++) {
- seq_printf(s, "Island: %-32s\tState: %s\n",
- pss_map[pss_index].name,
+ for (pss_index = 0; pss_map[pss_index].name; pss_index++) {
+ seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
+ pss_index, pss_map[pss_index].name,
pss_map[pss_index].bit_mask & pss ? "Off" : "On");
}
return 0;
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 3/5] x86: pmc_atom: supply register mappings via pmc object
2015-07-06 14:28 [PATCH v3 0/5] x86: pmc_atom: Add Cherrytrail support Andy Shevchenko
2015-07-06 14:29 ` [PATCH v3 1/5] x86: pmc_atom: export accessors to PMC registers Andy Shevchenko
2015-07-06 14:29 ` [PATCH v3 2/5] x86: pmc_atom: print index of device in loop Andy Shevchenko
@ 2015-07-06 14:29 ` Andy Shevchenko
2015-07-06 16:35 ` [tip:x86/platform] x86/platform/intel/pmc_atom: Supply register mappings via PMC object tip-bot for Andy Shevchenko
2015-07-06 14:29 ` [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface Andy Shevchenko
2015-07-06 14:29 ` [PATCH v3 5/5] x86: pmc_atom: place it under arch/x86/platform/atom Andy Shevchenko
4 siblings, 1 reply; 20+ messages in thread
From: Andy Shevchenko @ 2015-07-06 14:29 UTC (permalink / raw)
To: x86, Aubrey Li, Rafael J . Wysocki, Kumar P, Mahesh, linux-kernel,
linux-acpi, Ingo Molnar
Cc: Andy Shevchenko
The patch converts the functions to use the register mappings provided by pmc
object. It would help in case of mappings on different platforms.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/kernel/pmc_atom.c | 49 ++++++++++++++++++++++++++++++----------------
1 file changed, 32 insertions(+), 17 deletions(-)
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index c7dca07..4752b1a62 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -25,9 +25,20 @@
#include <asm/pmc_atom.h>
+struct pmc_bit_map {
+ const char *name;
+ u32 bit_mask;
+};
+
+struct pmc_reg_map {
+ const struct pmc_bit_map *dev;
+ const struct pmc_bit_map *pss;
+};
+
struct pmc_dev {
u32 base_addr;
void __iomem *regmap;
+ const struct pmc_reg_map *map;
#ifdef CONFIG_DEBUG_FS
struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
@@ -37,11 +48,6 @@ struct pmc_dev {
static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
-struct pmc_bit_map {
- const char *name;
- u32 bit_mask;
-};
-
static const struct pmc_bit_map dev_map[] = {
{"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
{"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
@@ -104,6 +110,11 @@ static const struct pmc_bit_map pss_map[] = {
{},
};
+static const struct pmc_reg_map reg_map = {
+ .dev = dev_map,
+ .pss = pss_map,
+};
+
static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
{
return readl(pmc->regmap + reg_offset);
@@ -172,17 +183,18 @@ static void pmc_hw_reg_setup(struct pmc_dev *pmc)
static int pmc_dev_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
+ const struct pmc_bit_map *map = pmc->map->dev;
u32 func_dis, func_dis_2, func_dis_index;
u32 d3_sts_0, d3_sts_1, d3_sts_index;
- int dev_index, reg_index;
+ int index, reg_index;
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
- for (dev_index = 0; dev_map[dev_index].name; dev_index++) {
- reg_index = dev_index / PMC_REG_BIT_WIDTH;
+ for (index = 0; map[index].name; index++) {
+ reg_index = index / PMC_REG_BIT_WIDTH;
if (reg_index) {
func_dis_index = func_dis_2;
d3_sts_index = d3_sts_1;
@@ -192,10 +204,10 @@ static int pmc_dev_state_show(struct seq_file *s, void *unused)
}
seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
- dev_index, dev_map[dev_index].name,
- dev_map[dev_index].bit_mask & func_dis_index ?
+ index, map[index].name,
+ map[index].bit_mask & func_dis_index ?
"Disabled" : "Enabled ",
- dev_map[dev_index].bit_mask & d3_sts_index ?
+ map[index].bit_mask & d3_sts_index ?
"D3" : "D0");
}
return 0;
@@ -216,13 +228,14 @@ static const struct file_operations pmc_dev_state_ops = {
static int pmc_pss_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
+ const struct pmc_bit_map *map = pmc->map->pss;
u32 pss = pmc_reg_read(pmc, PMC_PSS);
- int pss_index;
+ int index;
- for (pss_index = 0; pss_map[pss_index].name; pss_index++) {
+ for (index = 0; map[index].name; index++) {
seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
- pss_index, pss_map[pss_index].name,
- pss_map[pss_index].bit_mask & pss ? "Off" : "On");
+ index, map[index].name,
+ map[index].bit_mask & pss ? "Off" : "On");
}
return 0;
}
@@ -312,7 +325,7 @@ static int pmc_dbgfs_register(struct pmc_dev *pmc)
}
#endif /* CONFIG_DEBUG_FS */
-static int pmc_setup_dev(struct pci_dev *pdev)
+static int pmc_setup_dev(struct pci_dev *pdev, const struct pmc_reg_map *map)
{
struct pmc_dev *pmc = &pmc_device;
int ret;
@@ -334,6 +347,8 @@ static int pmc_setup_dev(struct pci_dev *pdev)
return -ENOMEM;
}
+ pmc->map = map;
+
/* PMC hardware registers setup */
pmc_hw_reg_setup(pmc);
@@ -376,7 +391,7 @@ static int __init pmc_atom_init(void)
for_each_pci_dev(pdev) {
ent = pci_match_id(pmc_pci_ids, pdev);
if (ent)
- return pmc_setup_dev(pdev);
+ return pmc_setup_dev(pdev, ®_map);
}
/* Device not found. */
return -ENODEV;
--
2.1.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [tip:x86/platform] x86/platform/intel/pmc_atom: Supply register mappings via PMC object
2015-07-06 14:29 ` [PATCH v3 3/5] x86: pmc_atom: supply register mappings via pmc object Andy Shevchenko
@ 2015-07-06 16:35 ` tip-bot for Andy Shevchenko
0 siblings, 0 replies; 20+ messages in thread
From: tip-bot for Andy Shevchenko @ 2015-07-06 16:35 UTC (permalink / raw)
To: linux-tip-commits
Cc: aubrey.li, mingo, rafael.j.wysocki, hpa, linux-kernel,
andriy.shevchenko, tglx, mahesh.kumar.p
Commit-ID: 940406d1cfb5b35cb9716d186fe3e6308f2700c5
Gitweb: http://git.kernel.org/tip/940406d1cfb5b35cb9716d186fe3e6308f2700c5
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Mon, 6 Jul 2015 17:29:02 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 6 Jul 2015 17:42:46 +0200
x86/platform/intel/pmc_atom: Supply register mappings via PMC object
The patch converts the functions to use the register mappings
provided by PMC object. It would help in case of mappings on
different platforms.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Link: http://lkml.kernel.org/r/1436192944-56496-4-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/pmc_atom.c | 49 ++++++++++++++++++++++++++++++----------------
1 file changed, 32 insertions(+), 17 deletions(-)
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index c7dca07..4752b1a62 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -25,9 +25,20 @@
#include <asm/pmc_atom.h>
+struct pmc_bit_map {
+ const char *name;
+ u32 bit_mask;
+};
+
+struct pmc_reg_map {
+ const struct pmc_bit_map *dev;
+ const struct pmc_bit_map *pss;
+};
+
struct pmc_dev {
u32 base_addr;
void __iomem *regmap;
+ const struct pmc_reg_map *map;
#ifdef CONFIG_DEBUG_FS
struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
@@ -37,11 +48,6 @@ struct pmc_dev {
static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
-struct pmc_bit_map {
- const char *name;
- u32 bit_mask;
-};
-
static const struct pmc_bit_map dev_map[] = {
{"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
{"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
@@ -104,6 +110,11 @@ static const struct pmc_bit_map pss_map[] = {
{},
};
+static const struct pmc_reg_map reg_map = {
+ .dev = dev_map,
+ .pss = pss_map,
+};
+
static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
{
return readl(pmc->regmap + reg_offset);
@@ -172,17 +183,18 @@ static void pmc_hw_reg_setup(struct pmc_dev *pmc)
static int pmc_dev_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
+ const struct pmc_bit_map *map = pmc->map->dev;
u32 func_dis, func_dis_2, func_dis_index;
u32 d3_sts_0, d3_sts_1, d3_sts_index;
- int dev_index, reg_index;
+ int index, reg_index;
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
- for (dev_index = 0; dev_map[dev_index].name; dev_index++) {
- reg_index = dev_index / PMC_REG_BIT_WIDTH;
+ for (index = 0; map[index].name; index++) {
+ reg_index = index / PMC_REG_BIT_WIDTH;
if (reg_index) {
func_dis_index = func_dis_2;
d3_sts_index = d3_sts_1;
@@ -192,10 +204,10 @@ static int pmc_dev_state_show(struct seq_file *s, void *unused)
}
seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
- dev_index, dev_map[dev_index].name,
- dev_map[dev_index].bit_mask & func_dis_index ?
+ index, map[index].name,
+ map[index].bit_mask & func_dis_index ?
"Disabled" : "Enabled ",
- dev_map[dev_index].bit_mask & d3_sts_index ?
+ map[index].bit_mask & d3_sts_index ?
"D3" : "D0");
}
return 0;
@@ -216,13 +228,14 @@ static const struct file_operations pmc_dev_state_ops = {
static int pmc_pss_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
+ const struct pmc_bit_map *map = pmc->map->pss;
u32 pss = pmc_reg_read(pmc, PMC_PSS);
- int pss_index;
+ int index;
- for (pss_index = 0; pss_map[pss_index].name; pss_index++) {
+ for (index = 0; map[index].name; index++) {
seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
- pss_index, pss_map[pss_index].name,
- pss_map[pss_index].bit_mask & pss ? "Off" : "On");
+ index, map[index].name,
+ map[index].bit_mask & pss ? "Off" : "On");
}
return 0;
}
@@ -312,7 +325,7 @@ static int pmc_dbgfs_register(struct pmc_dev *pmc)
}
#endif /* CONFIG_DEBUG_FS */
-static int pmc_setup_dev(struct pci_dev *pdev)
+static int pmc_setup_dev(struct pci_dev *pdev, const struct pmc_reg_map *map)
{
struct pmc_dev *pmc = &pmc_device;
int ret;
@@ -334,6 +347,8 @@ static int pmc_setup_dev(struct pci_dev *pdev)
return -ENOMEM;
}
+ pmc->map = map;
+
/* PMC hardware registers setup */
pmc_hw_reg_setup(pmc);
@@ -376,7 +391,7 @@ static int __init pmc_atom_init(void)
for_each_pci_dev(pdev) {
ent = pci_match_id(pmc_pci_ids, pdev);
if (ent)
- return pmc_setup_dev(pdev);
+ return pmc_setup_dev(pdev, ®_map);
}
/* Device not found. */
return -ENODEV;
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface
2015-07-06 14:28 [PATCH v3 0/5] x86: pmc_atom: Add Cherrytrail support Andy Shevchenko
` (2 preceding siblings ...)
2015-07-06 14:29 ` [PATCH v3 3/5] x86: pmc_atom: supply register mappings via pmc object Andy Shevchenko
@ 2015-07-06 14:29 ` Andy Shevchenko
2015-07-06 15:44 ` Ingo Molnar
` (2 more replies)
2015-07-06 14:29 ` [PATCH v3 5/5] x86: pmc_atom: place it under arch/x86/platform/atom Andy Shevchenko
4 siblings, 3 replies; 20+ messages in thread
From: Andy Shevchenko @ 2015-07-06 14:29 UTC (permalink / raw)
To: x86, Aubrey Li, Rafael J . Wysocki, Kumar P, Mahesh, linux-kernel,
linux-acpi, Ingo Molnar
Cc: Andy Shevchenko
The patch adds CHT PMC interface. This exposes all the South IP device power
states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
not aligned. This is fixed by splitting a common mapping on per register basis.
Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/include/asm/pmc_atom.h | 25 +++++++++
arch/x86/kernel/pmc_atom.c | 118 ++++++++++++++++++++++++++++++----------
2 files changed, 114 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
index 6ee2200..aa8744c 100644
--- a/arch/x86/include/asm/pmc_atom.h
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -18,6 +18,8 @@
/* ValleyView Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
+/* CherryTrail Power Control Unit PCI Device ID */
+#define PCI_DEVICE_ID_CHT_PMC 0x229C
/* PMC Memory mapped IO registers */
#define PMC_BASE_ADDR_OFFSET 0x44
@@ -29,6 +31,10 @@
#define PMC_FUNC_DIS 0x34
#define PMC_FUNC_DIS_2 0x38
+/* CHT specific bits in FUNC_DIS2 register */
+#define BIT_FD_GMM BIT(3)
+#define BIT_FD_ISH BIT(4)
+
/* S0ix wake event control */
#define PMC_S0IX_WAKE_EN 0x3C
@@ -75,6 +81,21 @@
#define PMC_PSS_BIT_USB BIT(16)
#define PMC_PSS_BIT_USB_SUS BIT(17)
+/* CHT specific bits in PSS register */
+#define PMC_PSS_BIT_CHT_UFS BIT(7)
+#define PMC_PSS_BIT_CHT_UXD BIT(11)
+#define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
+#define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
+#define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
+#define PMC_PSS_BIT_CHT_GMM BIT(17)
+#define PMC_PSS_BIT_CHT_ISH BIT(18)
+#define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
+
/* These registers reflect D3 status of functions */
#define PMC_D3_STS_0 0xA0
@@ -117,6 +138,10 @@
#define BIT_USH_SS_PHY BIT(2)
#define BIT_DFX BIT(3)
+/* CHT specific bits in PMC_D3_STS_1 register */
+#define BIT_STS_GMM BIT(1)
+#define BIT_STS_ISH BIT(2)
+
/* PMC I/O Registers */
#define ACPI_BASE_ADDR_OFFSET 0x40
#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index 4752b1a62..e814d34 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -31,7 +31,10 @@ struct pmc_bit_map {
};
struct pmc_reg_map {
- const struct pmc_bit_map *dev;
+ const struct pmc_bit_map *d3_sts_0;
+ const struct pmc_bit_map *d3_sts_1;
+ const struct pmc_bit_map *func_dis;
+ const struct pmc_bit_map *func_dis_2;
const struct pmc_bit_map *pss;
};
@@ -48,7 +51,7 @@ struct pmc_dev {
static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
-static const struct pmc_bit_map dev_map[] = {
+static const struct pmc_bit_map d3_sts_0_map[] = {
{"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
{"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
{"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
@@ -81,6 +84,10 @@ static const struct pmc_bit_map dev_map[] = {
{"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
{"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
{"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
+ {},
+};
+
+static struct pmc_bit_map byt_d3_sts_1_map[] = {
{"SMB", BIT_SMB},
{"OTG_SS_PHY", BIT_OTG_SS_PHY},
{"USH_SS_PHY", BIT_USH_SS_PHY},
@@ -88,7 +95,21 @@ static const struct pmc_bit_map dev_map[] = {
{},
};
-static const struct pmc_bit_map pss_map[] = {
+static struct pmc_bit_map cht_d3_sts_1_map[] = {
+ {"SMB", BIT_SMB},
+ {"GMM", BIT_STS_GMM},
+ {"ISH", BIT_STS_ISH},
+ {},
+};
+
+static struct pmc_bit_map cht_func_dis_2_map[] = {
+ {"SMB", BIT_SMB},
+ {"GMM", BIT_FD_GMM},
+ {"ISH", BIT_FD_ISH},
+ {},
+};
+
+static const struct pmc_bit_map byt_pss_map[] = {
{"GBE", PMC_PSS_BIT_GBE},
{"SATA", PMC_PSS_BIT_SATA},
{"HDA", PMC_PSS_BIT_HDA},
@@ -110,9 +131,43 @@ static const struct pmc_bit_map pss_map[] = {
{},
};
-static const struct pmc_reg_map reg_map = {
- .dev = dev_map,
- .pss = pss_map,
+static const struct pmc_bit_map cht_pss_map[] = {
+ {"SATA", PMC_PSS_BIT_SATA},
+ {"HDA", PMC_PSS_BIT_HDA},
+ {"SEC", PMC_PSS_BIT_SEC},
+ {"PCIE", PMC_PSS_BIT_PCIE},
+ {"LPSS", PMC_PSS_BIT_LPSS},
+ {"LPE", PMC_PSS_BIT_LPE},
+ {"UFS", PMC_PSS_BIT_CHT_UFS},
+ {"UXD", PMC_PSS_BIT_CHT_UXD},
+ {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
+ {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
+ {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
+ {"GMM", PMC_PSS_BIT_CHT_GMM},
+ {"ISH", PMC_PSS_BIT_CHT_ISH},
+ {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
+ {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
+ {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
+ {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
+ {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
+ {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
+ {},
+};
+
+static const struct pmc_reg_map byt_reg_map = {
+ .d3_sts_0 = d3_sts_0_map,
+ .d3_sts_1 = byt_d3_sts_1_map,
+ .func_dis = d3_sts_0_map,
+ .func_dis_2 = byt_d3_sts_1_map,
+ .pss = byt_pss_map,
+};
+
+static const struct pmc_reg_map cht_reg_map = {
+ .d3_sts_0 = d3_sts_0_map,
+ .d3_sts_1 = cht_d3_sts_1_map,
+ .func_dis = d3_sts_0_map,
+ .func_dis_2 = cht_func_dis_2_map,
+ .pss = cht_pss_map,
};
static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
@@ -180,36 +235,39 @@ static void pmc_hw_reg_setup(struct pmc_dev *pmc)
}
#ifdef CONFIG_DEBUG_FS
+static void pmc_dev_state_print(struct seq_file *s, int reg_index,
+ u32 sts, const struct pmc_bit_map *sts_map,
+ u32 fd, const struct pmc_bit_map *fd_map)
+{
+ int offset = PMC_REG_BIT_WIDTH * reg_index;
+ int index;
+
+ for (index = 0; sts_map[index].name; index++) {
+ seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
+ offset + index, sts_map[index].name,
+ fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
+ sts_map[index].bit_mask & sts ? "D3" : "D0");
+ }
+}
+
static int pmc_dev_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
- const struct pmc_bit_map *map = pmc->map->dev;
- u32 func_dis, func_dis_2, func_dis_index;
- u32 d3_sts_0, d3_sts_1, d3_sts_index;
- int index, reg_index;
+ const struct pmc_reg_map *m = pmc->map;
+ u32 func_dis, func_dis_2;
+ u32 d3_sts_0, d3_sts_1;
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
- for (index = 0; map[index].name; index++) {
- reg_index = index / PMC_REG_BIT_WIDTH;
- if (reg_index) {
- func_dis_index = func_dis_2;
- d3_sts_index = d3_sts_1;
- } else {
- func_dis_index = func_dis;
- d3_sts_index = d3_sts_0;
- }
+ /* Low part */
+ pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
+
+ /* High part */
+ pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
- seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
- index, map[index].name,
- map[index].bit_mask & func_dis_index ?
- "Disabled" : "Enabled ",
- map[index].bit_mask & d3_sts_index ?
- "D3" : "D0");
- }
return 0;
}
@@ -325,9 +383,10 @@ static int pmc_dbgfs_register(struct pmc_dev *pmc)
}
#endif /* CONFIG_DEBUG_FS */
-static int pmc_setup_dev(struct pci_dev *pdev, const struct pmc_reg_map *map)
+static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct pmc_dev *pmc = &pmc_device;
+ const struct pmc_reg_map *map = (struct pmc_reg_map *)ent->driver_data;
int ret;
/* Obtain ACPI base address */
@@ -369,7 +428,8 @@ static int pmc_setup_dev(struct pci_dev *pdev, const struct pmc_reg_map *map)
* a driver on the same PCI id.
*/
static const struct pci_device_id pmc_pci_ids[] = {
- { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_reg_map },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_reg_map },
{ 0, },
};
@@ -391,7 +451,7 @@ static int __init pmc_atom_init(void)
for_each_pci_dev(pdev) {
ent = pci_match_id(pmc_pci_ids, pdev);
if (ent)
- return pmc_setup_dev(pdev, ®_map);
+ return pmc_setup_dev(pdev, ent);
}
/* Device not found. */
return -ENODEV;
--
2.1.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface
2015-07-06 14:29 ` [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface Andy Shevchenko
@ 2015-07-06 15:44 ` Ingo Molnar
2015-07-06 15:47 ` Thomas Gleixner
2015-07-06 16:35 ` [tip:x86/platform] x86/platform/intel/pmc_atom: " tip-bot for Kumar P Mahesh
2015-07-06 16:51 ` tip-bot for Andy Shevchenko
2 siblings, 1 reply; 20+ messages in thread
From: Ingo Molnar @ 2015-07-06 15:44 UTC (permalink / raw)
To: Andy Shevchenko
Cc: x86, Aubrey Li, Rafael J . Wysocki, Kumar P, Mahesh, linux-kernel,
linux-acpi
* Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> The patch adds CHT PMC interface. This exposes all the South IP device power
> states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> not aligned. This is fixed by splitting a common mapping on per register basis.
>
> Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
That's a weird signoff sequence. I changed it to:
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Thanks,
Ingo
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface
2015-07-06 15:44 ` Ingo Molnar
@ 2015-07-06 15:47 ` Thomas Gleixner
2015-07-06 15:50 ` Ingo Molnar
0 siblings, 1 reply; 20+ messages in thread
From: Thomas Gleixner @ 2015-07-06 15:47 UTC (permalink / raw)
To: Ingo Molnar
Cc: Andy Shevchenko, x86, Aubrey Li, Rafael J . Wysocki,
Kumar P, Mahesh, linux-kernel, linux-acpi
On Mon, 6 Jul 2015, Ingo Molnar wrote:
> * Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
>
> > The patch adds CHT PMC interface. This exposes all the South IP device power
> > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> > not aligned. This is fixed by splitting a common mapping on per register basis.
> >
> > Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> That's a weird signoff sequence. I changed it to:
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Acked-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
It might lack a From: Kumar ...
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface
2015-07-06 15:47 ` Thomas Gleixner
@ 2015-07-06 15:50 ` Ingo Molnar
2015-07-06 16:37 ` Andy Shevchenko
0 siblings, 1 reply; 20+ messages in thread
From: Ingo Molnar @ 2015-07-06 15:50 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Andy Shevchenko, x86, Aubrey Li, Rafael J . Wysocki,
Kumar P, Mahesh, linux-kernel, linux-acpi
* Thomas Gleixner <tglx@linutronix.de> wrote:
> On Mon, 6 Jul 2015, Ingo Molnar wrote:
>
> > * Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> >
> > > The patch adds CHT PMC interface. This exposes all the South IP device power
> > > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> > > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> > > not aligned. This is fixed by splitting a common mapping on per register basis.
> > >
> > > Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >
> > That's a weird signoff sequence. I changed it to:
> >
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Acked-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
>
> It might lack a From: Kumar ...
Yeah, and got lost due to a rebase. Will change it to that, to preserve
authorship. Won't push it out before I hear back from Andy though.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface
2015-07-06 15:50 ` Ingo Molnar
@ 2015-07-06 16:37 ` Andy Shevchenko
2015-07-06 16:39 ` Ingo Molnar
0 siblings, 1 reply; 20+ messages in thread
From: Andy Shevchenko @ 2015-07-06 16:37 UTC (permalink / raw)
To: Ingo Molnar
Cc: Thomas Gleixner, Andy Shevchenko, x86@kernel.org, Aubrey Li,
Rafael J . Wysocki, Kumar P, Mahesh, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org
On Mon, Jul 6, 2015 at 6:50 PM, Ingo Molnar <mingo@kernel.org> wrote:
>
> * Thomas Gleixner <tglx@linutronix.de> wrote:
>
>> On Mon, 6 Jul 2015, Ingo Molnar wrote:
>>
>> > * Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
>> >
>> > > The patch adds CHT PMC interface. This exposes all the South IP device power
>> > > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
>> > > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
>> > > not aligned. This is fixed by splitting a common mapping on per register basis.
>> > >
>> > > Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
>> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> >
>> > That's a weird signoff sequence. I changed it to:
>> >
>> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> > Acked-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
>>
>> It might lack a From: Kumar ...
>
> Yeah, and got lost due to a rebase. Will change it to that, to preserve
> authorship. Won't push it out before I hear back from Andy though.
To clarify: "It's based on the previous work done by Kumar P Mahesh."
and we can remove SoB. It's quite far from the code initially taken
from Kumar.
Would you like me to update the commit message accordingly?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface
2015-07-06 16:37 ` Andy Shevchenko
@ 2015-07-06 16:39 ` Ingo Molnar
0 siblings, 0 replies; 20+ messages in thread
From: Ingo Molnar @ 2015-07-06 16:39 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Thomas Gleixner, Andy Shevchenko, x86@kernel.org, Aubrey Li,
Rafael J . Wysocki, Kumar P, Mahesh, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org
* Andy Shevchenko <andy.shevchenko@gmail.com> wrote:
> On Mon, Jul 6, 2015 at 6:50 PM, Ingo Molnar <mingo@kernel.org> wrote:
> >
> > * Thomas Gleixner <tglx@linutronix.de> wrote:
> >
> >> On Mon, 6 Jul 2015, Ingo Molnar wrote:
> >>
> >> > * Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> >> >
> >> > > The patch adds CHT PMC interface. This exposes all the South IP device power
> >> > > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> >> > > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> >> > > not aligned. This is fixed by splitting a common mapping on per register basis.
> >> > >
> >> > > Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> >> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >> >
> >> > That's a weird signoff sequence. I changed it to:
> >> >
> >> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >> > Acked-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> >>
> >> It might lack a From: Kumar ...
> >
> > Yeah, and got lost due to a rebase. Will change it to that, to preserve
> > authorship. Won't push it out before I hear back from Andy though.
>
> To clarify: "It's based on the previous work done by Kumar P Mahesh."
> and we can remove SoB. It's quite far from the code initially taken
> from Kumar.
>
> Would you like me to update the commit message accordingly?
Ok.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 20+ messages in thread
* [tip:x86/platform] x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
2015-07-06 14:29 ` [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface Andy Shevchenko
2015-07-06 15:44 ` Ingo Molnar
@ 2015-07-06 16:35 ` tip-bot for Kumar P Mahesh
2015-07-06 19:09 ` Peter Zijlstra
2015-07-06 16:51 ` tip-bot for Andy Shevchenko
2 siblings, 1 reply; 20+ messages in thread
From: tip-bot for Kumar P Mahesh @ 2015-07-06 16:35 UTC (permalink / raw)
To: linux-tip-commits
Cc: mahesh.kumar.p, tglx, linux-kernel, torvalds, peterz, hpa,
aubrey.li, mingo, andriy.shevchenko, rafael.j.wysocki
Commit-ID: daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
Gitweb: http://git.kernel.org/tip/daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
Author: Kumar P Mahesh <mahesh.kumar.p@intel.com>
AuthorDate: Mon, 6 Jul 2015 17:29:03 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 6 Jul 2015 17:50:59 +0200
x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
The patch adds CHT PMC interface. This exposes all the South IP
device power states and S0ix states for CHT. The bit map of
FUNC_DIS and D3_STS_0 registers for SoCs are consistent. The
D3_STS_1 and FUNC_DIS_2 registers, however, are not aligned.
This is fixed by splitting a common mapping on per register basis.
Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/pmc_atom.h | 25 +++++++++
arch/x86/kernel/pmc_atom.c | 118 ++++++++++++++++++++++++++++++----------
2 files changed, 114 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
index 6ee2200..aa8744c 100644
--- a/arch/x86/include/asm/pmc_atom.h
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -18,6 +18,8 @@
/* ValleyView Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
+/* CherryTrail Power Control Unit PCI Device ID */
+#define PCI_DEVICE_ID_CHT_PMC 0x229C
/* PMC Memory mapped IO registers */
#define PMC_BASE_ADDR_OFFSET 0x44
@@ -29,6 +31,10 @@
#define PMC_FUNC_DIS 0x34
#define PMC_FUNC_DIS_2 0x38
+/* CHT specific bits in FUNC_DIS2 register */
+#define BIT_FD_GMM BIT(3)
+#define BIT_FD_ISH BIT(4)
+
/* S0ix wake event control */
#define PMC_S0IX_WAKE_EN 0x3C
@@ -75,6 +81,21 @@
#define PMC_PSS_BIT_USB BIT(16)
#define PMC_PSS_BIT_USB_SUS BIT(17)
+/* CHT specific bits in PSS register */
+#define PMC_PSS_BIT_CHT_UFS BIT(7)
+#define PMC_PSS_BIT_CHT_UXD BIT(11)
+#define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
+#define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
+#define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
+#define PMC_PSS_BIT_CHT_GMM BIT(17)
+#define PMC_PSS_BIT_CHT_ISH BIT(18)
+#define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
+
/* These registers reflect D3 status of functions */
#define PMC_D3_STS_0 0xA0
@@ -117,6 +138,10 @@
#define BIT_USH_SS_PHY BIT(2)
#define BIT_DFX BIT(3)
+/* CHT specific bits in PMC_D3_STS_1 register */
+#define BIT_STS_GMM BIT(1)
+#define BIT_STS_ISH BIT(2)
+
/* PMC I/O Registers */
#define ACPI_BASE_ADDR_OFFSET 0x40
#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index 4752b1a62..e814d34 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -31,7 +31,10 @@ struct pmc_bit_map {
};
struct pmc_reg_map {
- const struct pmc_bit_map *dev;
+ const struct pmc_bit_map *d3_sts_0;
+ const struct pmc_bit_map *d3_sts_1;
+ const struct pmc_bit_map *func_dis;
+ const struct pmc_bit_map *func_dis_2;
const struct pmc_bit_map *pss;
};
@@ -48,7 +51,7 @@ struct pmc_dev {
static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
-static const struct pmc_bit_map dev_map[] = {
+static const struct pmc_bit_map d3_sts_0_map[] = {
{"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
{"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
{"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
@@ -81,6 +84,10 @@ static const struct pmc_bit_map dev_map[] = {
{"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
{"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
{"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
+ {},
+};
+
+static struct pmc_bit_map byt_d3_sts_1_map[] = {
{"SMB", BIT_SMB},
{"OTG_SS_PHY", BIT_OTG_SS_PHY},
{"USH_SS_PHY", BIT_USH_SS_PHY},
@@ -88,7 +95,21 @@ static const struct pmc_bit_map dev_map[] = {
{},
};
-static const struct pmc_bit_map pss_map[] = {
+static struct pmc_bit_map cht_d3_sts_1_map[] = {
+ {"SMB", BIT_SMB},
+ {"GMM", BIT_STS_GMM},
+ {"ISH", BIT_STS_ISH},
+ {},
+};
+
+static struct pmc_bit_map cht_func_dis_2_map[] = {
+ {"SMB", BIT_SMB},
+ {"GMM", BIT_FD_GMM},
+ {"ISH", BIT_FD_ISH},
+ {},
+};
+
+static const struct pmc_bit_map byt_pss_map[] = {
{"GBE", PMC_PSS_BIT_GBE},
{"SATA", PMC_PSS_BIT_SATA},
{"HDA", PMC_PSS_BIT_HDA},
@@ -110,9 +131,43 @@ static const struct pmc_bit_map pss_map[] = {
{},
};
-static const struct pmc_reg_map reg_map = {
- .dev = dev_map,
- .pss = pss_map,
+static const struct pmc_bit_map cht_pss_map[] = {
+ {"SATA", PMC_PSS_BIT_SATA},
+ {"HDA", PMC_PSS_BIT_HDA},
+ {"SEC", PMC_PSS_BIT_SEC},
+ {"PCIE", PMC_PSS_BIT_PCIE},
+ {"LPSS", PMC_PSS_BIT_LPSS},
+ {"LPE", PMC_PSS_BIT_LPE},
+ {"UFS", PMC_PSS_BIT_CHT_UFS},
+ {"UXD", PMC_PSS_BIT_CHT_UXD},
+ {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
+ {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
+ {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
+ {"GMM", PMC_PSS_BIT_CHT_GMM},
+ {"ISH", PMC_PSS_BIT_CHT_ISH},
+ {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
+ {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
+ {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
+ {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
+ {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
+ {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
+ {},
+};
+
+static const struct pmc_reg_map byt_reg_map = {
+ .d3_sts_0 = d3_sts_0_map,
+ .d3_sts_1 = byt_d3_sts_1_map,
+ .func_dis = d3_sts_0_map,
+ .func_dis_2 = byt_d3_sts_1_map,
+ .pss = byt_pss_map,
+};
+
+static const struct pmc_reg_map cht_reg_map = {
+ .d3_sts_0 = d3_sts_0_map,
+ .d3_sts_1 = cht_d3_sts_1_map,
+ .func_dis = d3_sts_0_map,
+ .func_dis_2 = cht_func_dis_2_map,
+ .pss = cht_pss_map,
};
static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
@@ -180,36 +235,39 @@ static void pmc_hw_reg_setup(struct pmc_dev *pmc)
}
#ifdef CONFIG_DEBUG_FS
+static void pmc_dev_state_print(struct seq_file *s, int reg_index,
+ u32 sts, const struct pmc_bit_map *sts_map,
+ u32 fd, const struct pmc_bit_map *fd_map)
+{
+ int offset = PMC_REG_BIT_WIDTH * reg_index;
+ int index;
+
+ for (index = 0; sts_map[index].name; index++) {
+ seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
+ offset + index, sts_map[index].name,
+ fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
+ sts_map[index].bit_mask & sts ? "D3" : "D0");
+ }
+}
+
static int pmc_dev_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
- const struct pmc_bit_map *map = pmc->map->dev;
- u32 func_dis, func_dis_2, func_dis_index;
- u32 d3_sts_0, d3_sts_1, d3_sts_index;
- int index, reg_index;
+ const struct pmc_reg_map *m = pmc->map;
+ u32 func_dis, func_dis_2;
+ u32 d3_sts_0, d3_sts_1;
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
- for (index = 0; map[index].name; index++) {
- reg_index = index / PMC_REG_BIT_WIDTH;
- if (reg_index) {
- func_dis_index = func_dis_2;
- d3_sts_index = d3_sts_1;
- } else {
- func_dis_index = func_dis;
- d3_sts_index = d3_sts_0;
- }
+ /* Low part */
+ pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
+
+ /* High part */
+ pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
- seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
- index, map[index].name,
- map[index].bit_mask & func_dis_index ?
- "Disabled" : "Enabled ",
- map[index].bit_mask & d3_sts_index ?
- "D3" : "D0");
- }
return 0;
}
@@ -325,9 +383,10 @@ static int pmc_dbgfs_register(struct pmc_dev *pmc)
}
#endif /* CONFIG_DEBUG_FS */
-static int pmc_setup_dev(struct pci_dev *pdev, const struct pmc_reg_map *map)
+static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct pmc_dev *pmc = &pmc_device;
+ const struct pmc_reg_map *map = (struct pmc_reg_map *)ent->driver_data;
int ret;
/* Obtain ACPI base address */
@@ -369,7 +428,8 @@ static int pmc_setup_dev(struct pci_dev *pdev, const struct pmc_reg_map *map)
* a driver on the same PCI id.
*/
static const struct pci_device_id pmc_pci_ids[] = {
- { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_reg_map },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_reg_map },
{ 0, },
};
@@ -391,7 +451,7 @@ static int __init pmc_atom_init(void)
for_each_pci_dev(pdev) {
ent = pci_match_id(pmc_pci_ids, pdev);
if (ent)
- return pmc_setup_dev(pdev, ®_map);
+ return pmc_setup_dev(pdev, ent);
}
/* Device not found. */
return -ENODEV;
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [tip:x86/platform] x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
2015-07-06 16:35 ` [tip:x86/platform] x86/platform/intel/pmc_atom: " tip-bot for Kumar P Mahesh
@ 2015-07-06 19:09 ` Peter Zijlstra
2015-07-07 6:55 ` Ingo Molnar
0 siblings, 1 reply; 20+ messages in thread
From: Peter Zijlstra @ 2015-07-06 19:09 UTC (permalink / raw)
To: linux-kernel, torvalds, mahesh.kumar.p, tglx, rafael.j.wysocki,
andriy.shevchenko, hpa, mingo, aubrey.li
Cc: linux-tip-commits
On Mon, Jul 06, 2015 at 09:35:33AM -0700, tip-bot for Kumar P Mahesh wrote:
> Commit-ID: daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
> Gitweb: http://git.kernel.org/tip/daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
> Author: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> AuthorDate: Mon, 6 Jul 2015 17:29:03 +0300
> Committer: Ingo Molnar <mingo@kernel.org>
> CommitDate: Mon, 6 Jul 2015 17:50:59 +0200
>
> x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
>
> The patch adds CHT PMC interface. This exposes all the South IP
> device power states and S0ix states for CHT. The bit map of
> FUNC_DIS and D3_STS_0 registers for SoCs are consistent. The
> D3_STS_1 and FUNC_DIS_2 registers, however, are not aligned.
> This is fixed by splitting a common mapping on per register basis.
TLA collision.. I thought this was about performance monitor counters :/
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [tip:x86/platform] x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
2015-07-06 19:09 ` Peter Zijlstra
@ 2015-07-07 6:55 ` Ingo Molnar
0 siblings, 0 replies; 20+ messages in thread
From: Ingo Molnar @ 2015-07-07 6:55 UTC (permalink / raw)
To: Peter Zijlstra
Cc: linux-kernel, torvalds, mahesh.kumar.p, tglx, rafael.j.wysocki,
andriy.shevchenko, hpa, aubrey.li, linux-tip-commits
* Peter Zijlstra <peterz@infradead.org> wrote:
> On Mon, Jul 06, 2015 at 09:35:33AM -0700, tip-bot for Kumar P Mahesh wrote:
> > Commit-ID: daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
> > Gitweb: http://git.kernel.org/tip/daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
> > Author: Kumar P Mahesh <mahesh.kumar.p@intel.com>
> > AuthorDate: Mon, 6 Jul 2015 17:29:03 +0300
> > Committer: Ingo Molnar <mingo@kernel.org>
> > CommitDate: Mon, 6 Jul 2015 17:50:59 +0200
> >
> > x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
> >
> > The patch adds CHT PMC interface. This exposes all the South IP device power
> > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> > not aligned. This is fixed by splitting a common mapping on per register
> > basis.
>
> TLA collision.. I thought this was about performance monitor counters :/
I had to look twice as well - but PMC as 'Power Management Controller' in used in
the kernel consistently in a number of places.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 20+ messages in thread
* [tip:x86/platform] x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
2015-07-06 14:29 ` [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface Andy Shevchenko
2015-07-06 15:44 ` Ingo Molnar
2015-07-06 16:35 ` [tip:x86/platform] x86/platform/intel/pmc_atom: " tip-bot for Kumar P Mahesh
@ 2015-07-06 16:51 ` tip-bot for Andy Shevchenko
2 siblings, 0 replies; 20+ messages in thread
From: tip-bot for Andy Shevchenko @ 2015-07-06 16:51 UTC (permalink / raw)
To: linux-tip-commits
Cc: aubrey.li, torvalds, tglx, hpa, rafael.j.wysocki,
andriy.shevchenko, linux-kernel, mingo, peterz
Commit-ID: 2b8f8eddaf05c02bb4a21db5be1691e36e242c65
Gitweb: http://git.kernel.org/tip/2b8f8eddaf05c02bb4a21db5be1691e36e242c65
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Mon, 6 Jul 2015 17:29:03 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 6 Jul 2015 18:39:38 +0200
x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
The patch adds CHT PMC interface. This exposes all the South IP
device power states and S0ix states for CHT. The bit map of
FUNC_DIS and D3_STS_0 registers for SoCs are consistent. The
D3_STS_1 and FUNC_DIS_2 registers, however, are not aligned.
This is fixed by splitting a common mapping on per register basis.
(Originally based on code from Kumar P Mahesh.)
Originally-from: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/pmc_atom.h | 25 +++++++++
arch/x86/kernel/pmc_atom.c | 118 ++++++++++++++++++++++++++++++----------
2 files changed, 114 insertions(+), 29 deletions(-)
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
index 6ee2200..aa8744c 100644
--- a/arch/x86/include/asm/pmc_atom.h
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -18,6 +18,8 @@
/* ValleyView Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
+/* CherryTrail Power Control Unit PCI Device ID */
+#define PCI_DEVICE_ID_CHT_PMC 0x229C
/* PMC Memory mapped IO registers */
#define PMC_BASE_ADDR_OFFSET 0x44
@@ -29,6 +31,10 @@
#define PMC_FUNC_DIS 0x34
#define PMC_FUNC_DIS_2 0x38
+/* CHT specific bits in FUNC_DIS2 register */
+#define BIT_FD_GMM BIT(3)
+#define BIT_FD_ISH BIT(4)
+
/* S0ix wake event control */
#define PMC_S0IX_WAKE_EN 0x3C
@@ -75,6 +81,21 @@
#define PMC_PSS_BIT_USB BIT(16)
#define PMC_PSS_BIT_USB_SUS BIT(17)
+/* CHT specific bits in PSS register */
+#define PMC_PSS_BIT_CHT_UFS BIT(7)
+#define PMC_PSS_BIT_CHT_UXD BIT(11)
+#define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
+#define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
+#define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
+#define PMC_PSS_BIT_CHT_GMM BIT(17)
+#define PMC_PSS_BIT_CHT_ISH BIT(18)
+#define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
+#define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
+
/* These registers reflect D3 status of functions */
#define PMC_D3_STS_0 0xA0
@@ -117,6 +138,10 @@
#define BIT_USH_SS_PHY BIT(2)
#define BIT_DFX BIT(3)
+/* CHT specific bits in PMC_D3_STS_1 register */
+#define BIT_STS_GMM BIT(1)
+#define BIT_STS_ISH BIT(2)
+
/* PMC I/O Registers */
#define ACPI_BASE_ADDR_OFFSET 0x40
#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index 4752b1a62..e814d34 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -31,7 +31,10 @@ struct pmc_bit_map {
};
struct pmc_reg_map {
- const struct pmc_bit_map *dev;
+ const struct pmc_bit_map *d3_sts_0;
+ const struct pmc_bit_map *d3_sts_1;
+ const struct pmc_bit_map *func_dis;
+ const struct pmc_bit_map *func_dis_2;
const struct pmc_bit_map *pss;
};
@@ -48,7 +51,7 @@ struct pmc_dev {
static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
-static const struct pmc_bit_map dev_map[] = {
+static const struct pmc_bit_map d3_sts_0_map[] = {
{"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
{"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
{"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
@@ -81,6 +84,10 @@ static const struct pmc_bit_map dev_map[] = {
{"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
{"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
{"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
+ {},
+};
+
+static struct pmc_bit_map byt_d3_sts_1_map[] = {
{"SMB", BIT_SMB},
{"OTG_SS_PHY", BIT_OTG_SS_PHY},
{"USH_SS_PHY", BIT_USH_SS_PHY},
@@ -88,7 +95,21 @@ static const struct pmc_bit_map dev_map[] = {
{},
};
-static const struct pmc_bit_map pss_map[] = {
+static struct pmc_bit_map cht_d3_sts_1_map[] = {
+ {"SMB", BIT_SMB},
+ {"GMM", BIT_STS_GMM},
+ {"ISH", BIT_STS_ISH},
+ {},
+};
+
+static struct pmc_bit_map cht_func_dis_2_map[] = {
+ {"SMB", BIT_SMB},
+ {"GMM", BIT_FD_GMM},
+ {"ISH", BIT_FD_ISH},
+ {},
+};
+
+static const struct pmc_bit_map byt_pss_map[] = {
{"GBE", PMC_PSS_BIT_GBE},
{"SATA", PMC_PSS_BIT_SATA},
{"HDA", PMC_PSS_BIT_HDA},
@@ -110,9 +131,43 @@ static const struct pmc_bit_map pss_map[] = {
{},
};
-static const struct pmc_reg_map reg_map = {
- .dev = dev_map,
- .pss = pss_map,
+static const struct pmc_bit_map cht_pss_map[] = {
+ {"SATA", PMC_PSS_BIT_SATA},
+ {"HDA", PMC_PSS_BIT_HDA},
+ {"SEC", PMC_PSS_BIT_SEC},
+ {"PCIE", PMC_PSS_BIT_PCIE},
+ {"LPSS", PMC_PSS_BIT_LPSS},
+ {"LPE", PMC_PSS_BIT_LPE},
+ {"UFS", PMC_PSS_BIT_CHT_UFS},
+ {"UXD", PMC_PSS_BIT_CHT_UXD},
+ {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
+ {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
+ {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
+ {"GMM", PMC_PSS_BIT_CHT_GMM},
+ {"ISH", PMC_PSS_BIT_CHT_ISH},
+ {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
+ {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
+ {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
+ {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
+ {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
+ {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
+ {},
+};
+
+static const struct pmc_reg_map byt_reg_map = {
+ .d3_sts_0 = d3_sts_0_map,
+ .d3_sts_1 = byt_d3_sts_1_map,
+ .func_dis = d3_sts_0_map,
+ .func_dis_2 = byt_d3_sts_1_map,
+ .pss = byt_pss_map,
+};
+
+static const struct pmc_reg_map cht_reg_map = {
+ .d3_sts_0 = d3_sts_0_map,
+ .d3_sts_1 = cht_d3_sts_1_map,
+ .func_dis = d3_sts_0_map,
+ .func_dis_2 = cht_func_dis_2_map,
+ .pss = cht_pss_map,
};
static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
@@ -180,36 +235,39 @@ static void pmc_hw_reg_setup(struct pmc_dev *pmc)
}
#ifdef CONFIG_DEBUG_FS
+static void pmc_dev_state_print(struct seq_file *s, int reg_index,
+ u32 sts, const struct pmc_bit_map *sts_map,
+ u32 fd, const struct pmc_bit_map *fd_map)
+{
+ int offset = PMC_REG_BIT_WIDTH * reg_index;
+ int index;
+
+ for (index = 0; sts_map[index].name; index++) {
+ seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
+ offset + index, sts_map[index].name,
+ fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
+ sts_map[index].bit_mask & sts ? "D3" : "D0");
+ }
+}
+
static int pmc_dev_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
- const struct pmc_bit_map *map = pmc->map->dev;
- u32 func_dis, func_dis_2, func_dis_index;
- u32 d3_sts_0, d3_sts_1, d3_sts_index;
- int index, reg_index;
+ const struct pmc_reg_map *m = pmc->map;
+ u32 func_dis, func_dis_2;
+ u32 d3_sts_0, d3_sts_1;
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
- for (index = 0; map[index].name; index++) {
- reg_index = index / PMC_REG_BIT_WIDTH;
- if (reg_index) {
- func_dis_index = func_dis_2;
- d3_sts_index = d3_sts_1;
- } else {
- func_dis_index = func_dis;
- d3_sts_index = d3_sts_0;
- }
+ /* Low part */
+ pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
+
+ /* High part */
+ pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
- seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
- index, map[index].name,
- map[index].bit_mask & func_dis_index ?
- "Disabled" : "Enabled ",
- map[index].bit_mask & d3_sts_index ?
- "D3" : "D0");
- }
return 0;
}
@@ -325,9 +383,10 @@ static int pmc_dbgfs_register(struct pmc_dev *pmc)
}
#endif /* CONFIG_DEBUG_FS */
-static int pmc_setup_dev(struct pci_dev *pdev, const struct pmc_reg_map *map)
+static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct pmc_dev *pmc = &pmc_device;
+ const struct pmc_reg_map *map = (struct pmc_reg_map *)ent->driver_data;
int ret;
/* Obtain ACPI base address */
@@ -369,7 +428,8 @@ static int pmc_setup_dev(struct pci_dev *pdev, const struct pmc_reg_map *map)
* a driver on the same PCI id.
*/
static const struct pci_device_id pmc_pci_ids[] = {
- { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_reg_map },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_reg_map },
{ 0, },
};
@@ -391,7 +451,7 @@ static int __init pmc_atom_init(void)
for_each_pci_dev(pdev) {
ent = pci_match_id(pmc_pci_ids, pdev);
if (ent)
- return pmc_setup_dev(pdev, ®_map);
+ return pmc_setup_dev(pdev, ent);
}
/* Device not found. */
return -ENODEV;
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 5/5] x86: pmc_atom: place it under arch/x86/platform/atom
2015-07-06 14:28 [PATCH v3 0/5] x86: pmc_atom: Add Cherrytrail support Andy Shevchenko
` (3 preceding siblings ...)
2015-07-06 14:29 ` [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface Andy Shevchenko
@ 2015-07-06 14:29 ` Andy Shevchenko
2015-07-06 16:35 ` [tip:x86/platform] x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom tip-bot for Andy Shevchenko
2015-07-06 16:51 ` tip-bot for Andy Shevchenko
4 siblings, 2 replies; 20+ messages in thread
From: Andy Shevchenko @ 2015-07-06 14:29 UTC (permalink / raw)
To: x86, Aubrey Li, Rafael J . Wysocki, Kumar P, Mahesh, linux-kernel,
linux-acpi, Ingo Molnar
Cc: Andy Shevchenko
This is specific driver for Intel Atom SoCs like BayTrail and Braswell. Let's
move it to dedicated folder and alleviate a arch/x86/kernel burden.
There is no functional change.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/kernel/Makefile | 1 -
arch/x86/platform/atom/Makefile | 3 ++-
arch/x86/{kernel => platform/atom}/pmc_atom.c | 0
3 files changed, 2 insertions(+), 2 deletions(-)
rename arch/x86/{kernel => platform/atom}/pmc_atom.c (100%)
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 0f15af4..81db53b 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -108,7 +108,6 @@ obj-$(CONFIG_EFI) += sysfb_efi.o
obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
obj-$(CONFIG_TRACING) += tracepoint.o
obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
-obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
###
# 64 bit specific files
diff --git a/arch/x86/platform/atom/Makefile b/arch/x86/platform/atom/Makefile
index 0a3a40c..40983f5 100644
--- a/arch/x86/platform/atom/Makefile
+++ b/arch/x86/platform/atom/Makefile
@@ -1 +1,2 @@
-obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
+obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
+obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/platform/atom/pmc_atom.c
similarity index 100%
rename from arch/x86/kernel/pmc_atom.c
rename to arch/x86/platform/atom/pmc_atom.c
--
2.1.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [tip:x86/platform] x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom
2015-07-06 14:29 ` [PATCH v3 5/5] x86: pmc_atom: place it under arch/x86/platform/atom Andy Shevchenko
@ 2015-07-06 16:35 ` tip-bot for Andy Shevchenko
2015-07-06 16:51 ` tip-bot for Andy Shevchenko
1 sibling, 0 replies; 20+ messages in thread
From: tip-bot for Andy Shevchenko @ 2015-07-06 16:35 UTC (permalink / raw)
To: linux-tip-commits
Cc: mahesh.kumar.p, torvalds, mingo, tglx, aubrey.li, peterz,
rafael.j.wysocki, hpa, andriy.shevchenko, linux-kernel
Commit-ID: d3889467c221b5c40cd6499b805eacce4c739cd1
Gitweb: http://git.kernel.org/tip/d3889467c221b5c40cd6499b805eacce4c739cd1
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Mon, 6 Jul 2015 17:29:04 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 6 Jul 2015 17:51:00 +0200
x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom
This is specific driver for Intel Atom SoCs like BayTrail and
Braswell. Let's move it to dedicated folder and alleviate a
arch/x86/kernel burden.
There is no functional change.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1436192944-56496-6-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/Makefile | 1 -
arch/x86/platform/atom/Makefile | 3 ++-
arch/x86/{kernel => platform/atom}/pmc_atom.c | 0
3 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 0f15af4..81db53b 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -108,7 +108,6 @@ obj-$(CONFIG_EFI) += sysfb_efi.o
obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
obj-$(CONFIG_TRACING) += tracepoint.o
obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
-obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
###
# 64 bit specific files
diff --git a/arch/x86/platform/atom/Makefile b/arch/x86/platform/atom/Makefile
index 0a3a40c..40983f5 100644
--- a/arch/x86/platform/atom/Makefile
+++ b/arch/x86/platform/atom/Makefile
@@ -1 +1,2 @@
-obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
+obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
+obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/platform/atom/pmc_atom.c
similarity index 100%
rename from arch/x86/kernel/pmc_atom.c
rename to arch/x86/platform/atom/pmc_atom.c
^ permalink raw reply related [flat|nested] 20+ messages in thread* [tip:x86/platform] x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom
2015-07-06 14:29 ` [PATCH v3 5/5] x86: pmc_atom: place it under arch/x86/platform/atom Andy Shevchenko
2015-07-06 16:35 ` [tip:x86/platform] x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom tip-bot for Andy Shevchenko
@ 2015-07-06 16:51 ` tip-bot for Andy Shevchenko
1 sibling, 0 replies; 20+ messages in thread
From: tip-bot for Andy Shevchenko @ 2015-07-06 16:51 UTC (permalink / raw)
To: linux-tip-commits
Cc: torvalds, aubrey.li, andriy.shevchenko, linux-kernel,
rafael.j.wysocki, peterz, tglx, mingo, hpa, mahesh.kumar.p
Commit-ID: 91780c41a9e03ca6c351a0b2152662139b94b274
Gitweb: http://git.kernel.org/tip/91780c41a9e03ca6c351a0b2152662139b94b274
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Mon, 6 Jul 2015 17:29:04 +0300
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 6 Jul 2015 18:39:38 +0200
x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom
This is specific driver for Intel Atom SoCs like BayTrail and
Braswell. Let's move it to dedicated folder and alleviate a
arch/x86/kernel burden.
There is no functional change.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1436192944-56496-6-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/Makefile | 1 -
arch/x86/platform/atom/Makefile | 3 ++-
arch/x86/{kernel => platform/atom}/pmc_atom.c | 0
3 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 0f15af4..81db53b 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -108,7 +108,6 @@ obj-$(CONFIG_EFI) += sysfb_efi.o
obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
obj-$(CONFIG_TRACING) += tracepoint.o
obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
-obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
###
# 64 bit specific files
diff --git a/arch/x86/platform/atom/Makefile b/arch/x86/platform/atom/Makefile
index 0a3a40c..40983f5 100644
--- a/arch/x86/platform/atom/Makefile
+++ b/arch/x86/platform/atom/Makefile
@@ -1 +1,2 @@
-obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
+obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
+obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/platform/atom/pmc_atom.c
similarity index 100%
rename from arch/x86/kernel/pmc_atom.c
rename to arch/x86/platform/atom/pmc_atom.c
^ permalink raw reply related [flat|nested] 20+ messages in thread