From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755118AbbGFMpo (ORCPT ); Mon, 6 Jul 2015 08:45:44 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:51078 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754550AbbGFMpm (ORCPT ); Mon, 6 Jul 2015 08:45:42 -0400 Date: Mon, 6 Jul 2015 20:45:28 +0800 From: Jisheng Zhang To: Thomas Gleixner CC: Sebastian Hesselbarth , Mark Rutland , Jason Cooper , LKML Subject: Re: [patch] irqchip/dw-apb-ictl: Fix generic domain chip wreckage Message-ID: <20150706204528.0eb416bc@xhacker> In-Reply-To: References: <20150706101543.373582262@linutronix.de> <20150706200736.3f8ef2b0@xhacker> <20150706203130.15404ad5@xhacker> X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-07-06_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 kscore.is_bulkscore=0 kscore.compositescore=1 compositescore=0.9 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 kscore.is_spamscore=0 rbsscore=0.9 spamscore=0 urlsuspectscore=0.9 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1506180000 definitions=main-1507060205 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 6 Jul 2015 14:36:40 +0200 Thomas Gleixner wrote: > On Mon, 6 Jul 2015, Jisheng Zhang wrote: > > > Thomas Gleixner wrote: > > the following patch seems fix the panic, but I dunno whether it's correct or not, > > could you please help to check? > > > > Thanks, > > Jisheng > > > > diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c > > index f4a0e11..8d996cb 100644 > > --- a/drivers/irqchip/irq-dw-apb-ictl.c > > +++ b/drivers/irqchip/irq-dw-apb-ictl.c > > @@ -30,13 +30,14 @@ > > static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc) > > { > > struct irq_domain *d = irq_desc_get_handler_data(desc); > > - struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0); > > + struct irq_chip_generic *gc; > > struct irq_chip *chip = irq_desc_get_chip(desc); > > int n; > > > > chained_irq_enter(chip, desc); > > > > - for (n = 0; n < d->gc->num_chips; n++, gc++) { > > + for (n = 0; n < d->gc->num_chips; n++) { > > + gc = irq_get_domain_generic_chip(d, n * 32); > > u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); > > Yes it's correct. Seems I tried to be overly clever by avoiding the > lookup of the second chip. Will fold back. > Great! Feel free to add my Tested-by. I'll also cherry-pick your patch into marvell internal repo. Thank you very much, Jisheng