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Date: Tue, 7 Jul 2015 08:55:26 +0200
From: Ingo Molnar <mingo@kernel.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: linux-kernel@vger.kernel.org, torvalds@linux-foundation.org,
        mahesh.kumar.p@intel.com, tglx@linutronix.de,
        rafael.j.wysocki@intel.com, andriy.shevchenko@linux.intel.com,
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        linux-tip-commits@vger.kernel.org
Subject: Re: [tip:x86/platform] x86/platform/intel/pmc_atom: Add Cherrytrail
 PMC interface
Message-ID: <20150707065526.GA9585@gmail.com>
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* Peter Zijlstra <peterz@infradead.org> wrote:

> On Mon, Jul 06, 2015 at 09:35:33AM -0700, tip-bot for Kumar P Mahesh wrote:
> > Commit-ID:  daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
> > Gitweb:     http://git.kernel.org/tip/daf61e1b7fc31d553fe3bf2dead95d9404ad0f57
> > Author:     Kumar P Mahesh <mahesh.kumar.p@intel.com>
> > AuthorDate: Mon, 6 Jul 2015 17:29:03 +0300
> > Committer:  Ingo Molnar <mingo@kernel.org>
> > CommitDate: Mon, 6 Jul 2015 17:50:59 +0200
> > 
> > x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
> > 
> > The patch adds CHT PMC interface. This exposes all the South IP device power 
> > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers 
> > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are 
> > not aligned. This is fixed by splitting a common mapping on per register 
> > basis.
> 
> TLA collision.. I thought this was about performance monitor counters :/

I had to look twice as well - but PMC as 'Power Management Controller' in used in 
the kernel consistently in a number of places.

Thanks,

	Ingo