From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751201AbbGMFqG (ORCPT ); Mon, 13 Jul 2015 01:46:06 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:37569 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751069AbbGMFqE (ORCPT ); Mon, 13 Jul 2015 01:46:04 -0400 Date: Mon, 13 Jul 2015 07:45:49 +0200 From: Sascha Hauer To: James Liao Cc: Matthias Brugger , Mike Turquette , Stephen Boyd , Heiko Stubner , srv_heupstream@mediatek.com, Daniel Kurtz , Ricky Liang , Rob Herring , Sascha Hauer , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH v3 0/3] Fixes for MT8173 PLLs Message-ID: <20150713054549.GC18700@pengutronix.de> References: <1436517574-17895-1-git-send-email-jamesjj.liao@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1436517574-17895-1-git-send-email-jamesjj.liao@mediatek.com> X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-IRC: #ptxdist @freenode X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-Uptime: 07:45:18 up 18 days, 6 min, 51 users, load average: 0.19, 0.21, 0.20 User-Agent: Mutt/1.5.21 (2010-09-15) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 10, 2015 at 04:39:31PM +0800, James Liao wrote: > Title changed. Previous title is "Add MT8173 MMPLL change rate support" > and can be found in [1]. > > This patchset contains some fixes for changing rate of PLLs, especially > for MMPLL. > > The first 2 patches are common fixes for PLLs, and the last patch is a > fix to support MT8173 MMPLL changing rate because its frequency setting > is different from other PLLs. > > changes since v2: > - Rebase to 4.2-rc1. > - Split fixes of PLL setting calculation to a separeted patch. > > changes since v1: > - Add a separated patch for mtk_pll_set_rate_regs(). > - Use a structure array to describe a div_table. > - Limit max frequency to div_table[0]. > - Minor changes such as static and comments. > > [1] https://lkml.org/lkml/2015/7/8/265 > > James Liao (3): > clk: mediatek: Fix PLL registers setting flow > clk: mediatek: Fix calculation of PLL rate settings > clk: mediatek: Add MT8173 MMPLL change rate support Acked-by: Sascha Hauer Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |