From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Jiang Liu <jiang.liu@linux.intel.com>,
linux-mips@linux-mips.org
Subject: [patch 09/12] MIPS/ath91: Remove pointless irqdisable/enable
Date: Mon, 13 Jul 2015 20:46:06 -0000 [thread overview]
Message-ID: <20150713200715.209383043@linutronix.de> (raw)
In-Reply-To: 20150713200602.799079101@linutronix.de
[-- Attachment #1: MIPS-ath91--Remove-pointless-irqdisable-enable.patch --]
[-- Type: text/plain, Size: 2502 bytes --]
The various interrupt flow handlers in ath79 are cascading interrupt
handlers. They all have a disable_irq_nosync()/enable_irq() pair
around the generic_handle_irq() call. The value of this disable/enable
is zero because its a complete noop:
disable_irq_nosync() merily increments the disable count without
actually masking the interrupt. enable_irq() soleley decrements the
disable count without touching the interrupt chip. The interrupt
cannot arrive again because the complete call chain runs with
interrupts disabled.
Remove it.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
---
arch/mips/ath79/irq.c | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
Index: tip/arch/mips/ath79/irq.c
===================================================================
--- tip.orig/arch/mips/ath79/irq.c
+++ tip/arch/mips/ath79/irq.c
@@ -124,8 +124,6 @@ static void ar934x_ip2_irq_dispatch(unsi
{
u32 status;
- disable_irq_nosync(irq);
-
status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
@@ -137,8 +135,6 @@ static void ar934x_ip2_irq_dispatch(unsi
} else {
spurious_interrupt();
}
-
- enable_irq(irq);
}
static void ar934x_ip2_irq_init(void)
@@ -157,14 +153,12 @@ static void qca955x_ip2_irq_dispatch(uns
{
u32 status;
- disable_irq_nosync(irq);
-
status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
if (status == 0) {
spurious_interrupt();
- goto enable;
+ return;
}
if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
@@ -176,17 +170,12 @@ static void qca955x_ip2_irq_dispatch(uns
/* TODO: flush DDR? */
generic_handle_irq(ATH79_IP2_IRQ(1));
}
-
-enable:
- enable_irq(irq);
}
static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
{
u32 status;
- disable_irq_nosync(irq);
-
status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
QCA955X_EXT_INT_USB1 |
@@ -194,7 +183,7 @@ static void qca955x_ip3_irq_dispatch(uns
if (status == 0) {
spurious_interrupt();
- goto enable;
+ return;
}
if (status & QCA955X_EXT_INT_USB1) {
@@ -211,9 +200,6 @@ static void qca955x_ip3_irq_dispatch(uns
/* TODO: flush DDR? */
generic_handle_irq(ATH79_IP3_IRQ(2));
}
-
-enable:
- enable_irq(irq);
}
static void qca955x_irq_init(void)
next prev parent reply other threads:[~2015-07-13 20:47 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-13 20:45 [patch 00/12] MIPS: Interrupt cleanups and API change preparation Thomas Gleixner
2015-07-13 20:45 ` [patch 01/12] MIPS/jz4740: Consolidate chained IRQ handler install/remove Thomas Gleixner
2015-07-13 20:45 ` [patch 02/12] MIPS/pci-ar71xx: " Thomas Gleixner
2015-07-13 20:45 ` [patch 03/12] MIPS/pci-ar724x: " Thomas Gleixner
2015-07-13 20:45 ` [patch 04/12] MIPS/pci-rt3883: " Thomas Gleixner
2015-07-13 20:50 ` Julia Lawall
2015-07-13 21:07 ` Thomas Gleixner
2015-07-13 20:45 ` [patch 05/12] MIPS/irq: Use access helper irq_data_get_affinity_mask() Thomas Gleixner
2015-07-13 20:46 ` [patch 06/12] MIPS/alchemy: Use irq_set_chip_handler_name_locked() Thomas Gleixner
2015-07-13 20:46 ` [patch 07/12] MIPS/bcm63xx: Use irq_set_handler_locked() Thomas Gleixner
2015-07-13 20:46 ` [patch 08/12] MIPS/alchemy: Remove pointless irqdisable/enable Thomas Gleixner
2015-07-14 6:00 ` Manuel Lauss
2015-07-14 8:16 ` Thomas Gleixner
2015-07-14 8:55 ` Manuel Lauss
2015-07-14 9:02 ` Ralf Baechle
2015-07-14 9:58 ` Thomas Gleixner
2015-07-13 20:46 ` Thomas Gleixner [this message]
2015-07-13 20:46 ` [patch 10/12] MIPS/cavium/octeon: Replace the homebrewn flow handler Thomas Gleixner
2015-07-15 21:19 ` David Daney
2015-07-13 20:46 ` [patch 11/12] MIPS/netlogic: Prepare ipi handlers for irq argument removal Thomas Gleixner
2015-07-13 20:46 ` [patch 12/12] MIPS/PCI/rt3883: Prepare rt3883_pci_irq_handler " Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150713200715.209383043@linutronix.de \
--to=tglx@linutronix.de \
--cc=jiang.liu@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox