Re: [tip:locking/core] locking/Documentation: Clarify failed cmpxchg( ) memory ordering semantics

Davidlohr Bueso
2015-08-03T17:37:09Z

On Mon, 2015-08-03 at 09:59 -0700, tip-bot for Will Deacon wrote:
> Commit-ID: ed2de9f74ecbbf3063d29b2334e7b455d7f35189
> Gitweb: http://git.kernel.org/tip/ed2de9f74ecbbf3063d29b2334e7b455d7f35189
> Author: Will Deacon <will.deacon@arm.com>
> AuthorDate: Thu, 16 Jul 2015 16:10:06 +0100
> Committer: Ingo Molnar <mingo@kernel.org>
> CommitDate: Mon, 3 Aug 2015 10:57:09 +0200
>
> locking/Documentation: Clarify failed cmpxchg() memory ordering semantics
>
> A failed cmpxchg does not provide any memory ordering guarantees, a
> property that is used to optimise the cmpxchg implementations on Alpha,
> PowerPC and arm64.
>
> This patch updates atomic_ops.txt and memory-barriers.txt to reflect
> this.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> Cc: Andrew Morton <akpm@linux-foundation.org>
> Cc: Davidlohr Bueso <dave@stgolabs.net>
> Cc: Douglas Hatch <doug.hatch@hp.com>
> Cc: H. Peter Anvin <hpa@zytor.com>
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: Linus Torvalds <torvalds@linux-foundation.org>
> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Scott J Norton <scott.norton@hp.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Waiman Long <waiman.long@hp.com>
> Link: http://lkml.kernel.org/r/20150716151006.GH26390@arm.com
> Signed-off-by: Ingo Molnar <mingo@kernel.org>
> ---
> Documentation/atomic_ops.txt | 4 +++-
> Documentation/memory-barriers.txt | 6 +++---
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/atomic_ops.txt b/Documentation/atomic_ops.txt
> index dab6da3..b19fc34 100644
> --- a/Documentation/atomic_ops.txt
> +++ b/Documentation/atomic_ops.txt
> @@ -266,7 +266,9 @@ with the given old and new values. Like all atomic_xxx operations,
> atomic_cmpxchg will only satisfy its atomicity semantics as long as all
> other accesses of *v are performed through atomic_xxx operations.
>
> -atomic_cmpxchg must provide explicit memory barriers around the operation.
> +atomic_cmpxchg must provide explicit memory barriers around the operation,
> +although if the comparison fails then no memory ordering guarantees are
> +required.

Thanks, I also stumbled upon this with the wake-q stuff.