Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake

[Andi Kleen <andi@firstfloor.org>]

On Fri, Jul 17, 2015 at 01:41:04PM -0700, Stephane Eranian wrote:
> Andi,
> 
> On Fri, Jul 17, 2015 at 1:09 PM, Andi Kleen <ak@linux.intel.com> wrote:
> >> I believe this mask of 0x3fff17 is wrong and should instead be
> >> 0x7fffff based on the description of the FRONTEND
> >> MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some
> >> valid latency values may be rejected.
> >
> > No, my mask is correct.
> >
> Ok, so your event mask (0x17) really only allows what's defined
> instead the full width of the field.
> 
> As for the IDQ_BUBBLE_WIDTH, you only allow 2 bits out of 3, so
> maximum bubble threshold is 3
> instead of 7. I assume this is because you know that it cannot have
> more than 3 simultaneously then.
> 
> Would be good to explain this a bit more in the code.

I don't think the code is the right place to document such registers.
I can ask for the SDM to be clarified. But if you follow the documented
events you will never set any undefined bits, so you won't need to care
about this. We just have to exclude it at the kernel level to avoid #GP crashes
if someone is writing random values.

-Andi