From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753783AbbGRArz (ORCPT ); Fri, 17 Jul 2015 20:47:55 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36722 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751901AbbGRArx (ORCPT ); Fri, 17 Jul 2015 20:47:53 -0400 Date: Fri, 17 Jul 2015 17:47:49 -0700 From: Stephen Boyd To: James Liao Cc: Matthias Brugger , Mike Turquette , Heiko Stubner , srv_heupstream@mediatek.com, Daniel Kurtz , Ricky Liang , Rob Herring , Sascha Hauer , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH v3 1/3] clk: mediatek: Fix PLL registers setting flow Message-ID: <20150718004749.GV30412@codeaurora.org> References: <1436517574-17895-1-git-send-email-jamesjj.liao@mediatek.com> <1436517574-17895-2-git-send-email-jamesjj.liao@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1436517574-17895-2-git-send-email-jamesjj.liao@mediatek.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/10, James Liao wrote: > Write postdiv and pcw settings at the same time for PLLs if postdiv > and pcw settings are on the same register. > > This is need by PLLs such as MT8173 MMPLL and ARM*PLL. > > Signed-off-by: James Liao > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project