Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake

[Andi Kleen <ak@linux.intel.com>]

On Fri, Jul 17, 2015 at 04:52:56PM -0700, Stephane Eranian wrote:
> On Fri, Jul 17, 2015 at 4:31 PM, Andi Kleen <ak@linux.intel.com> wrote:
> > On Fri, Jul 17, 2015 at 03:00:18PM -0700, Stephane Eranian wrote:
> >> Andi,
> >>
> >> On Fri, Jul 17, 2015 at 2:19 PM, Andi Kleen <ak@linux.intel.com> wrote:
> >> >> But then, the SDM is misleading. It is not describing what's
> >> >> implemented for SKL.
> >> >
> >> > Actually it has a list of valid values you can put into the various fields.
> >> > None of them have the bits set you're trying to set.
> >> >
> >> You are talking about the events (bit 0-7). I am talking about the bubble
> >> thresholds. I am okay with the event list for bits 0-7.
> >
> > Fair enough. There's a one-off in the MSR table and table 18-54. The IDQ
> > bubble width is only 21:20. I'll ask for that to be fixed in both places
> > that document them.
> >
> There is still something broken here, if bit 22 is not implemented,
> then you have
> a bunch of frontend events in the SKL event table (download.01.org) which are
> bogus:

I double checked and bit 22 is actually implemented. I'll send a patch to 
update the mask in the driver. Thanks for the report.

-Andi