Re: Re: [V2 PATCH 1/3] x86/panic: Fix re-entrance problem due to panic on NMI

Michal Hocko
2015-07-30T07:55:19Z

On Thu 30-07-15 07:33:15, 河合英宏 / KAWAI，HIDEHIRO wrote:
[...]
> Are you using SGI UV? On that platform, NMIs may be delivered to
> all cpus because LVT1 of all cpus are not masked as follows:

This is Compute Blade 520XB1 from Hitachi with 240 cpus.

--
Michal Hocko
SUSE Labs