From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755003AbbG3Kky (ORCPT ); Thu, 30 Jul 2015 06:40:54 -0400 Received: from bombadil.infradead.org ([198.137.202.9]:56386 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751177AbbG3Kkx (ORCPT ); Thu, 30 Jul 2015 06:40:53 -0400 Date: Thu, 30 Jul 2015 12:40:46 +0200 From: Peter Zijlstra To: Alexander Shishkin Cc: Ingo Molnar , linux-kernel@vger.kernel.org, adrian.hunter@intel.com, x86@kernel.org, hpa@zytor.com, acme@infradead.org Subject: Re: [PATCH 1/3] perf/x86/intel/pt: Add new timing packet enables Message-ID: <20150730104046.GV19282@twins.programming.kicks-ass.net> References: <1437140050-23363-1-git-send-email-alexander.shishkin@linux.intel.com> <1437140050-23363-2-git-send-email-alexander.shishkin@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1437140050-23363-2-git-send-email-alexander.shishkin@linux.intel.com> User-Agent: Mutt/1.5.21 (2012-12-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 17, 2015 at 04:34:08PM +0300, Alexander Shishkin wrote: > +#define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \ > + RTIT_CTL_DISRETC | \ > + RTIT_CTL_CYCLEACC | \ > + RTIT_CTL_MTC_EN | \ > + RTIT_CTL_MTC_RANGE | \ > + RTIT_CTL_CYC_THRESH | \ > + RTIT_CTL_PSB_FREQ) > #define RTIT_CTL_CYC (RTIT_CTL_CYCLEACC | \ RTIT_CTL_CYC_THRESH | \ RTIT_CTL_PSB_FREQ) #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \ RTIT_CTL_MTC_RANGE) #define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \ RTIT_CTL_DISRETC | \ RTIT_CTL_CYC | \ RTIT_CTL_MTC) > static bool pt_event_valid(struct perf_event *event) > { > u64 config = event->attr.config; > + u64 allowed, requested; > > if ((config & PT_CONFIG_MASK) != config) > return false; > > + if (config & > + (RTIT_CTL_CYCLEACC | RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ)) { if (config & RTIT_CTL_CYC) { > + if (!pt_cap_get(PT_CAP_psb_cyc)) > + return false; > + > + allowed = pt_cap_get(PT_CAP_psb_periods); > + requested = (config & RTIT_CTL_PSB_FREQ) >> > + RTIT_CTL_PSB_FREQ_OFFSET; > + if (requested && (!(allowed & BIT(requested)))) > + return false; > + > + allowed = pt_cap_get(PT_CAP_cycle_thresholds); > + requested = (config & RTIT_CTL_CYC_THRESH) >> > + RTIT_CTL_CYC_THRESH_OFFSET; > + if (requested && (!(allowed & BIT(requested)))) > + return false; > + } > + > + if (config & (RTIT_CTL_MTC_EN | RTIT_CTL_MTC_RANGE)) { if (config & RTIT_CTL_MTC) { > + allowed = pt_cap_get(PT_CAP_mtc_periods); > + > + if (!allowed) > + return false; > + > + requested = (config & RTIT_CTL_MTC_RANGE) >> > + RTIT_CTL_MTC_RANGE_OFFSET; > + > + if (!(allowed & BIT(requested))) > + return false; > + } > + > return true; > } Would that make sense?