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Date: Thu, 30 Jul 2015 14:14:35 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>, linux-kernel@vger.kernel.org,
        adrian.hunter@intel.com, x86@kernel.org, hpa@zytor.com,
        acme@infradead.org
Subject: Re: [PATCH 1/3] perf/x86/intel/pt: Add new timing packet enables
Message-ID: <20150730121435.GJ25159@twins.programming.kicks-ass.net>
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On Thu, Jul 30, 2015 at 02:57:17PM +0300, Alexander Shishkin wrote:
> Peter Zijlstra <peterz@infradead.org> writes:
> 
> > On Fri, Jul 17, 2015 at 04:34:08PM +0300, Alexander Shishkin wrote:
> >> +#define PT_CONFIG_MASK (RTIT_CTL_TSC_EN     |	\
> >> +			RTIT_CTL_DISRETC    |	\
> >> +			RTIT_CTL_CYCLEACC   |	\
> >> +			RTIT_CTL_MTC_EN     |	\
> >> +			RTIT_CTL_MTC_RANGE  |	\
> >> +			RTIT_CTL_CYC_THRESH |   \
> >> +			RTIT_CTL_PSB_FREQ)
> >>  
> >
> > #define RTIT_CTL_CYC (RTIT_CTL_CYCLEACC   | \
> > 		      RTIT_CTL_CYC_THRESH | \
> > 		      RTIT_CTL_PSB_FREQ)
> 
> PSB_FREQ is not, strictly speaking, related to cycle accurate mode. Both
> adjustable psb frequency and cycle accurate mode settings are enumerated
> with the same CPUID bit, but they really do different things unrelated
> to one another.

RTIT_CTL_CYC_PSB then, to match the CPUID bit name?

> >> +	if (config & (RTIT_CTL_MTC_EN | RTIT_CTL_MTC_RANGE)) {
> >
> > 	if (config & RTIT_CTL_MTC) {
> >
> > Would that make sense?
> 
> To me either way is fine. Want me to respin it?

Please.