Re: [tip:perf/core] perf/x86: Add an MSR PMU driver

Andy Lutomirski
2015-08-04T14:50:44Z

On Tue, Aug 4, 2015 at 2:01 AM, tip-bot for Andy Lutomirski
<tipbot@zytor.com> wrote:
> Commit-ID: b7b7c7821d932ba18ef6c8eafc8536066b4c2ef4
> Gitweb: http://git.kernel.org/tip/b7b7c7821d932ba18ef6c8eafc8536066b4c2ef4
> Author: Andy Lutomirski <luto@kernel.org>

I think I'm slightly late to the party reviewing what appears to be my
own code :)

> --- /dev/null
> +++ b/arch/x86/kernel/cpu/perf_event_msr.c
> @@ -0,0 +1,242 @@
> +#include <linux/perf_event.h>
> +
> +enum perf_msr_id {
> + PERF_MSR_TSC = 0,
> + PERF_MSR_APERF = 1,
> + PERF_MSR_MPERF = 2,
> + PERF_MSR_PPERF = 3,
> + PERF_MSR_SMI = 4,
> +
> + PERF_MSR_EVENT_MAX,
> +};
> +
> +struct perf_msr {
> + int id;
> + u64 msr;
> +};
> +
> +static struct perf_msr msr[] = {
> + { PERF_MSR_TSC, 0 },
> + { PERF_MSR_APERF, MSR_IA32_APERF },
> + { PERF_MSR_MPERF, MSR_IA32_MPERF },
> + { PERF_MSR_PPERF, MSR_PPERF },
> + { PERF_MSR_SMI, MSR_SMI_COUNT },
> +};

I think this could be easier to work with if it were [PERF_MSR_TSC] =
{...}, etc. No big deal, though, until the list gets long. However,
it might make fixing the apparent issue below easier...

> +static int msr_event_init(struct perf_event *event)
> +{
> + u64 cfg = event->attr.config;

...

> + event->hw.event_base = msr[cfg].msr;

Shouldn't this verify that the fancy enumeration code actually
believes that msr[cfg] exists on this system? Otherwise we might have
a very short wait until the perf fuzzer oopses this thing :)

--Andy