From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933207AbbHKXyy (ORCPT ); Tue, 11 Aug 2015 19:54:54 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:44830 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932512AbbHKXyx (ORCPT ); Tue, 11 Aug 2015 19:54:53 -0400 Date: Tue, 11 Aug 2015 16:54:52 -0700 From: Stephen Boyd To: dinguyen@opensource.altera.com Cc: mturquette@baylibre.com, dinh.linux@gmail.com, linux-kernel@vger.kernel.org Subject: Re: [PATCHv2] clk: socfpga: Add a second parent option for the dbg_base_clk Message-ID: <20150811235451.GA26614@codeaurora.org> References: <1437795018-27601-1-git-send-email-dinguyen@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1437795018-27601-1-git-send-email-dinguyen@opensource.altera.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/24, dinguyen@opensource.altera.com wrote: > From: Dinh Nguyen > > The debug base clock can be bypassed from the main PLL to the OSC1 clock. > The bypass register is the staysoc1(0x10) register that is in the clock > manager. > > This patch adds the option to get the correct parent for the debug base > clock. > > Signed-off-by: Dinh Nguyen > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project