From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752722AbbHaIPd (ORCPT ); Mon, 31 Aug 2015 04:15:33 -0400 Received: from mail-wi0-f169.google.com ([209.85.212.169]:36819 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752536AbbHaIPa (ORCPT ); Mon, 31 Aug 2015 04:15:30 -0400 Date: Mon, 31 Aug 2015 10:15:26 +0200 From: Ingo Molnar To: "Michael S. Tsirkin" Cc: "H. Peter Anvin" , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , x86@kernel.org, Rusty Russell , Linus Torvalds Subject: Re: [PATCH 1/2] x86/bitops: implement __test_bit Message-ID: <20150831081526.GB9974@gmail.com> References: <1440776707-22016-1-git-send-email-mst@redhat.com> <20150831060549.GB7093@gmail.com> <0779C35A-141F-4019-942A-CD3F861048A3@zytor.com> <20150831105355-mutt-send-email-mst@redhat.com> <20150831075947.GA9974@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150831075947.GA9974@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Ingo Molnar wrote: > > Disassembly of section .text: > > > > 00000000 <__variable_test_bit>: > > __variable_test_bit(): > > 0: 8b 54 24 08 mov 0x8(%esp),%edx > > 4: 8b 44 24 04 mov 0x4(%esp),%eax > > 8: 0f a3 02 bt %eax,(%edx) > > b: 19 c0 sbb %eax,%eax > > d: c3 ret > > e: 66 90 xchg %ax,%ax > > > > 00000010 <__constant_test_bit>: > > __constant_test_bit(): > > 10: 8b 4c 24 04 mov 0x4(%esp),%ecx > > 14: 8b 44 24 08 mov 0x8(%esp),%eax > > 18: 89 ca mov %ecx,%edx > > 1a: c1 fa 04 sar $0x4,%edx > > 1d: 8b 04 90 mov (%eax,%edx,4),%eax > > 20: d3 e8 shr %cl,%eax > > 22: 83 e0 01 and $0x1,%eax > > 25: c3 ret > > But that's due to the forced interface of generating a return code. Please > compare it at an inlined usage site, where GCC is free to do the comparison > directly and use the result in flags. So I was thinking about the patch below on top of yours. But turns out GCC indeed generates worse code even under the best of circumstances. For example the nested_vmx_disable_intercept_for_msr() change: @@ -4275,24 +4275,24 @@ static void nested_vmx_disable_intercept */ if (msr <= 0x1fff) { if (type & MSR_TYPE_R && - !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) + !__test_bit(msr, msr_bitmap_l1 + 0x000 / f)) /* read-low */ __clear_bit(msr, msr_bitmap_nested + 0x000 / f); before (i.e. your series): ffffffff818b1082: 89 d0 mov %edx,%eax ffffffff818b1084: 48 0f a3 07 bt %rax,(%rdi) ffffffff818b1088: 45 19 c0 sbb %r8d,%r8d ffffffff818b108b: 45 85 c0 test %r8d,%r8d ffffffff818b108e: 75 04 jne ffffffff818b1094 after (with my 'optimization' patch applied): ffffffff818b1091: 89 d0 mov %edx,%eax ffffffff818b1093: 49 89 c0 mov %rax,%r8 ffffffff818b1096: 49 c1 f8 06 sar $0x6,%r8 ffffffff818b109a: 4e 8b 04 c7 mov (%rdi,%r8,8),%r8 ffffffff818b109e: 49 0f a3 d0 bt %rdx,%r8 ffffffff818b10a2: 72 04 jb ffffffff818b10a8 So GCC when left to its own devices, generates one more instruction and 4 more bytes. Why does GCC do that? Why doesn't it use BT directly and use the flag, i.e. something like [pseudocode]: ffffffff818b1082: 89 d0 mov %edx,%eax ffffffff818b1084: 48 0f a3 07 bt %rax,(%rdi) ffffffff818b108e: 75 04 jne ffffffff818b1094 ? In any case I take back my objection: Acked-by: Ingo Molnar Thanks, Ingo --- arch/x86/include/asm/bitops.h | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) Index: tip/arch/x86/include/asm/bitops.h =================================================================== --- tip.orig/arch/x86/include/asm/bitops.h +++ tip/arch/x86/include/asm/bitops.h @@ -323,24 +323,12 @@ static inline int variable_test_bit(long return oldbit; } -static __always_inline int __constant_test_bit(long nr, const unsigned long *addr) +static __always_inline int __test_bit(long nr, const unsigned long *addr) { return ((1UL << (nr & (BITS_PER_LONG-1))) & (addr[nr >> _BITOPS_LONG_SHIFT])) != 0; } -static inline int __variable_test_bit(long nr, const unsigned long *addr) -{ - int oldbit; - - asm volatile("bt %2,%1\n\t" - "sbb %0,%0" - : "=r" (oldbit) - : "m" (*addr), "Ir" (nr)); - - return oldbit; -} - #if 0 /* Fool kernel-doc since it doesn't do macros yet */ /** * test_bit - Determine whether a bit is set @@ -362,11 +350,6 @@ static int __test_bit(int nr, const vola ? constant_test_bit((nr), (addr)) \ : variable_test_bit((nr), (addr))) -#define __test_bit(nr, addr) \ - (__builtin_constant_p((nr)) \ - ? __constant_test_bit((nr), (addr)) \ - : __variable_test_bit((nr), (addr))) - /** * __ffs - find first set bit in word * @word: The word to search