From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753146AbbIAVpu (ORCPT ); Tue, 1 Sep 2015 17:45:50 -0400 Received: from e39.co.us.ibm.com ([32.97.110.160]:56895 "EHLO e39.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751725AbbIAVps (ORCPT ); Tue, 1 Sep 2015 17:45:48 -0400 X-Helo: d03dlp02.boulder.ibm.com X-MailFrom: paulmck@linux.vnet.ibm.com X-RcptTo: linux-kernel@vger.kernel.org Date: Tue, 1 Sep 2015 14:45:40 -0700 From: "Paul E. McKenney" To: Will Deacon Cc: Peter Zijlstra , Boqun Feng , "linux-kernel@vger.kernel.org" , "linuxppc-dev@lists.ozlabs.org" , Ingo Molnar , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Thomas Gleixner , Waiman Long Subject: Re: [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants Message-ID: <20150901214540.GI4029@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <1440730099-29133-1-git-send-email-boqun.feng@gmail.com> <1440730099-29133-4-git-send-email-boqun.feng@gmail.com> <20150828104854.GB16853@twins.programming.kicks-ass.net> <20150828120614.GC29325@fixme-laptop.cn.ibm.com> <20150828141602.GA924@fixme-laptop.cn.ibm.com> <20150828153921.GF19282@twins.programming.kicks-ass.net> <20150901190027.GP1612@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150901190027.GP1612@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15090121-0033-0000-0000-000005B6D83B Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 01, 2015 at 08:00:27PM +0100, Will Deacon wrote: > On Fri, Aug 28, 2015 at 04:39:21PM +0100, Peter Zijlstra wrote: > > On Fri, Aug 28, 2015 at 10:16:02PM +0800, Boqun Feng wrote: > > > Ah.. just read through the thread you mentioned, I might misunderstand > > > you, probably because I didn't understand RCpc well.. > > > > > > You are saying that in a RELEASE we -might- switch from smp_lwsync() to > > > smp_mb() semantically, right? I guess this means we -might- switch from > > > RCpc to RCsc, right? > > > > > > If so, I think I'd better to wait until we have a conclusion for this. > > > > Yes, the difference between RCpc and RCsc is in the meaning of RELEASE + > > ACQUIRE. With RCsc that implies a full memory barrier, with RCpc it does > > not. > > We've discussed this before, but for the sake of completeness, I don't > think we're fully RCsc either because we don't order the actual RELEASE > operation again a subsequent ACQUIRE operation: > > P0 > smp_store_release(&x, 1); > foo = smp_load_acquire(&y); > > P1 > smp_store_release(&y, 1); > bar = smp_load_acquire(&x); > > We allow foo == bar == 0, which is prohibited by SC. I certainly hope that no one expects foo == bar == 0 to be prohibited!!! On the other hand, in this case, foo == bar == 1 will be prohibited: P0 foo = smp_load_acquire(&y); smp_store_release(&x, 1); P1 bar = smp_load_acquire(&x); smp_store_release(&y, 1); > However, we *do* enforce ordering on any prior or subsequent accesses > for the code snippet above (the release and acquire combine to give a > full barrier), which makes these primitives well suited to things like > message passing. If I understand your example correctly, neither x86 nor Power implement a full barrier in this case. For example: P0 WRITE_ONCE(a, 1); smp_store_release(b, 1); r1 = smp_load_acquire(c); r2 = READ_ONCE(d); P1 WRITE_ONCE(d, 1); smp_mb(); r3 = READ_ONCE(a); Both x86 and Power can reorder P0 as follows: P0 r1 = smp_load_acquire(c); r2 = READ_ONCE(d); WRITE_ONCE(a, 1); smp_store_release(b, 1); Which clearly shows that the non-SC outcome r2 == 0 && r3 == 0 is allowed. Or am I missing your point here? Thanx, Paul