From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753438AbbIKRNq (ORCPT ); Fri, 11 Sep 2015 13:13:46 -0400 Received: from e31.co.us.ibm.com ([32.97.110.149]:60208 "EHLO e31.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752073AbbIKRNo (ORCPT ); Fri, 11 Sep 2015 13:13:44 -0400 X-Helo: d03dlp01.boulder.ibm.com X-MailFrom: paulmck@linux.vnet.ibm.com X-RcptTo: linux-kernel@vger.kernel.org Date: Fri, 11 Sep 2015 10:09:36 -0700 From: "Paul E. McKenney" To: Will Deacon Cc: Peter Zijlstra , Boqun Feng , "linux-kernel@vger.kernel.org" , "linuxppc-dev@lists.ozlabs.org" , Ingo Molnar , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Thomas Gleixner , Waiman Long Subject: Re: [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants Message-ID: <20150911170936.GV4029@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <1440730099-29133-1-git-send-email-boqun.feng@gmail.com> <1440730099-29133-4-git-send-email-boqun.feng@gmail.com> <20150828104854.GB16853@twins.programming.kicks-ass.net> <20150828120614.GC29325@fixme-laptop.cn.ibm.com> <20150828141602.GA924@fixme-laptop.cn.ibm.com> <20150828153921.GF19282@twins.programming.kicks-ass.net> <20150901190027.GP1612@arm.com> <20150901214540.GI4029@linux.vnet.ibm.com> <20150902095906.GC25720@arm.com> <20150911124507.GB16833@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150911124507.GB16833@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15091117-8236-0000-0000-00000F14B4C5 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 11, 2015 at 01:45:07PM +0100, Will Deacon wrote: > [left the context in the hope that we can make some progress] > > On Wed, Sep 02, 2015 at 10:59:06AM +0100, Will Deacon wrote: > > On Tue, Sep 01, 2015 at 10:45:40PM +0100, Paul E. McKenney wrote: > > > On Tue, Sep 01, 2015 at 08:00:27PM +0100, Will Deacon wrote: > > > > On Fri, Aug 28, 2015 at 04:39:21PM +0100, Peter Zijlstra wrote: > > > > > Yes, the difference between RCpc and RCsc is in the meaning of RELEASE + > > > > > ACQUIRE. With RCsc that implies a full memory barrier, with RCpc it does > > > > > not. > > > > > > > > We've discussed this before, but for the sake of completeness, I don't > > > > think we're fully RCsc either because we don't order the actual RELEASE > > > > operation again a subsequent ACQUIRE operation: > > > > > > > > P0 > > > > smp_store_release(&x, 1); > > > > foo = smp_load_acquire(&y); > > > > > > > > P1 > > > > smp_store_release(&y, 1); > > > > bar = smp_load_acquire(&x); > > > > > > > > We allow foo == bar == 0, which is prohibited by SC. > > > > > > I certainly hope that no one expects foo == bar == 0 to be prohibited!!! > > > > I just thought it was worth making this point, because it is prohibited > > in SC and I don't want people to think that our RELEASE/ACQUIRE operations > > are SC (even though they happen to be on arm64). > > > > > On the other hand, in this case, foo == bar == 1 will be prohibited: > > > > > > P0 > > > foo = smp_load_acquire(&y); > > > smp_store_release(&x, 1); > > > > > > P1 > > > bar = smp_load_acquire(&x); > > > smp_store_release(&y, 1); > > > > Agreed. > > > > > > However, we *do* enforce ordering on any prior or subsequent accesses > > > > for the code snippet above (the release and acquire combine to give a > > > > full barrier), which makes these primitives well suited to things like > > > > message passing. > > > > > > If I understand your example correctly, neither x86 nor Power implement > > > a full barrier in this case. For example: > > > > > > P0 > > > WRITE_ONCE(a, 1); > > > smp_store_release(b, 1); > > > r1 = smp_load_acquire(c); > > > r2 = READ_ONCE(d); > > > > > > P1 > > > WRITE_ONCE(d, 1); > > > smp_mb(); > > > r3 = READ_ONCE(a); > > > > > > Both x86 and Power can reorder P0 as follows: > > > > > > P0 > > > r1 = smp_load_acquire(c); > > > r2 = READ_ONCE(d); > > > WRITE_ONCE(a, 1); > > > smp_store_release(b, 1); > > > > > > Which clearly shows that the non-SC outcome r2 == 0 && r3 == 0 is allowed. > > > > > > Or am I missing your point here? > > > > I think this example is slightly different. Having the RELEASE/ACQUIRE > > operations being reordered with respect to each other is one thing, but > > I thought we were heading in a direction where they combined to give a > > full barrier with respect to other accesses. In that case, the reordering > > above would be forbidden. > > > > Peter -- if the above reordering can happen on x86, then moving away > > from RCpc is going to be less popular than I hoped... > > Peter, any thoughts? I'm not au fait with the x86 memory model, but what > Paul's saying is worrying. The herd tool has an x86 mode, which will allow you to double-check my scenario. This tool is described in "Herding Cats: Modelling, Simulation, Testing, and Data-mining for Weak Memory" by Alglave, Marenget, and Tautschnig. The herd tool is available at this git repository: https://github.com/herd/herdtools. Thanx, Paul