From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934224AbbIVS3H (ORCPT ); Tue, 22 Sep 2015 14:29:07 -0400 Received: from foss.arm.com ([217.140.101.70]:59651 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933514AbbIVS3E (ORCPT ); Tue, 22 Sep 2015 14:29:04 -0400 Date: Tue, 22 Sep 2015 19:29:02 +0100 From: Will Deacon To: Robert Richter Cc: Catalin Marinas , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Tirumalesh Chalamarla , Robert Richter Subject: Re: [PATCH] arm64: Increase the max granular size Message-ID: <20150922182902.GO7356@arm.com> References: <1442944788-17254-1-git-send-email-rric@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442944788-17254-1-git-send-email-rric@kernel.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 22, 2015 at 06:59:48PM +0100, Robert Richter wrote: > From: Tirumalesh Chalamarla > > Increase the standard cacheline size to avoid having locks in the same > cacheline. > > Cavium's ThunderX core implements cache lines of 128 byte size. With > current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could > share the same cache line leading a performance degradation. > Increasing the size fixes that. Do you have an example of that happening? > Increasing the size has no negative impact to cache invalidation on > systems with a smaller cache line. There is an impact on memory usage, > but that's not too important for arm64 use cases. Do you have any before/after numbers to show the impact of this change on other supported SoCs? Will