[PATCH 0/3] MIPS GIC fixes

[PATCH 0/3] MIPS GIC fixes

[Paul Burton]

This series fixes a couple of problems with the MIPS GIC support,
impacting systems with the 64 bit CM3 and those with multithreading and
non-contiguous numbering for VP(E)s across cores.

Paul Burton (3):
  MIPS: CM: provide a function to map from CPU to VP ID
  irqchip: mips-gic: convert CPU numbers to VP IDs
  irqchip: mips-gic: fix pending & mask reads for MIPS64 with 32b GIC

 arch/mips/include/asm/mips-cm.h | 39 +++++++++++++++++++++++++++++++++++++++
 drivers/irqchip/irq-mips-gic.c  | 12 ++++++++++--
 2 files changed, 49 insertions(+), 2 deletions(-)

-- 
2.5.3

[PATCH 1/3] MIPS: CM: provide a function to map from CPU to VP ID

[Paul Burton]

The VP ID of a given CPU may not match up with the CPU number used by
Linux. For example, if the width of the VP part of the VP ID is wider
than log2(number of VPs per core) and the system has multiple cores then
this will be the case. Alternatively, if a pre-r6 system implements the
MT ASE with multiple VPEs per core and Linux is built without support
for the MT ASE then the numbers won't match up either. Provide a
function to convert from CPU number to VP ID.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/include/asm/mips-cm.h | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index d75b75e..1f1927a 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -194,6 +194,7 @@ BUILD_CM_RW(reg3_mask,		MIPS_CM_GCB_OFS + 0xc8)
 BUILD_CM_R_(gic_status,		MIPS_CM_GCB_OFS + 0xd0)
 BUILD_CM_R_(cpc_status,		MIPS_CM_GCB_OFS + 0xf0)
 BUILD_CM_RW(l2_config,		MIPS_CM_GCB_OFS + 0x130)
+BUILD_CM_RW(sys_config2,	MIPS_CM_GCB_OFS + 0x150)
 
 /* Core Local & Core Other register accessor functions */
 BUILD_CM_Cx_RW(reset_release,	0x00)
@@ -316,6 +317,10 @@ BUILD_CM_Cx_R_(tcid_8_priority,	0x80)
 #define CM_GCR_L2_CONFIG_ASSOC_SHF		0
 #define CM_GCR_L2_CONFIG_ASSOC_MSK		(_ULCAST_(0xff) << 0)
 
+/* GCR_SYS_CONFIG2 register fields */
+#define CM_GCR_SYS_CONFIG2_MAXVPW_SHF		0
+#define CM_GCR_SYS_CONFIG2_MAXVPW_MSK		(_ULCAST_(0xf) << 0)
+
 /* GCR_Cx_COHERENCE register fields */
 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF	0
 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK	(_ULCAST_(0xff) << 0)
@@ -405,4 +410,38 @@ static inline int mips_cm_revision(void)
 	return read_gcr_rev();
 }
 
+/**
+ * mips_cm_max_vp_width() - return the width in bits of VP indices
+ *
+ * Return: the width, in bits, of VP indices in fields that combine core & VP
+ * indices.
+ */
+static inline unsigned int mips_cm_max_vp_width(void)
+{
+	extern int smp_num_siblings;
+
+	if (mips_cm_revision() >= CM_REV_CM3)
+		return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;
+
+	return smp_num_siblings;
+}
+
+/**
+ * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
+ * @cpu: the CPU whose VP ID to calculate
+ *
+ * Hardware such as the GIC uses identifiers for VPs which may not match the
+ * CPU numbers used by Linux. This function calculates the hardware VP
+ * identifier corresponding to a given CPU.
+ *
+ * Return: the VP ID for the CPU.
+ */
+static inline unsigned int mips_cm_vp_id(unsigned int cpu)
+{
+	unsigned int core = cpu_data[cpu].core;
+	unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
+
+	return (core * mips_cm_max_vp_width()) + vp;
+}
+
 #endif /* __MIPS_ASM_MIPS_CM_H__ */
-- 
2.5.3

[PATCH 2/3] irqchip: mips-gic: convert CPU numbers to VP IDs

[Paul Burton]

Make use of the mips_cm_vp_id function to convert from Linux CPU numbers
to the VP IDs used by hardware, which are not identical in all systems.
Without doing so we map interrupts to incorrect VP(E)s.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/irqchip/irq-mips-gic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index af2f16b..842a53d 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -426,7 +426,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 	spin_lock_irqsave(&gic_lock, flags);
 
 	/* Re-route this IRQ */
-	gic_map_to_vpe(irq, cpumask_first(&tmp));
+	gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp)));
 
 	/* Update the pcpu_masks */
 	for (i = 0; i < NR_CPUS; i++)
@@ -599,7 +599,7 @@ static __init void gic_ipi_init_one(unsigned int intr, int cpu,
 				      GIC_SHARED_TO_HWIRQ(intr));
 	int i;
 
-	gic_map_to_vpe(intr, cpu);
+	gic_map_to_vpe(intr, mips_cm_vp_id(cpu));
 	for (i = 0; i < NR_CPUS; i++)
 		clear_bit(intr, pcpu_masks[i].pcpu_mask);
 	set_bit(intr, pcpu_masks[cpu].pcpu_mask);
-- 
2.5.3

[PATCH 3/3] irqchip: mips-gic: fix pending & mask reads for MIPS64 with 32b GIC

[Paul Burton]

gic_handle_shared_int reads the GIC interrupt pending & mask registers
directly into a bitmap, which is defined as an array of unsigned longs.
The GIC pending registers may be 32 bits wide if the CM is older than
CM3, regardless of the bit width of the CPU, but for MIPS64 kernels
the unsigned longs in the bitmap will be 64 bits wide. In this case we
need to perform 2 x 32 bit reads per 64 bit unsigned long in order to
avoid missing interrupts.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/irqchip/irq-mips-gic.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 842a53d..aeaa061 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -320,6 +320,14 @@ static void gic_handle_shared_int(bool chained)
 		intrmask[i] = gic_read(intrmask_reg);
 		pending_reg += gic_reg_step;
 		intrmask_reg += gic_reg_step;
+
+		if (!config_enabled(CONFIG_64BIT) || mips_cm_is64)
+			continue;
+
+		pending[i] |= (u64)gic_read(pending_reg) << 32;
+		intrmask[i] |= (u64)gic_read(intrmask_reg) << 32;
+		pending_reg += gic_reg_step;
+		intrmask_reg += gic_reg_step;
 	}
 
 	bitmap_and(pending, pending, intrmask, gic_shared_intrs);
-- 
2.5.3

Re: [PATCH 0/3] MIPS GIC fixes

[Thomas Gleixner]

On Tue, 22 Sep 2015, Paul Burton wrote:

> This series fixes a couple of problems with the MIPS GIC support,
> impacting systems with the 64 bit CM3 and those with multithreading and
> non-contiguous numbering for VP(E)s across cores.
> 
> Paul Burton (3):
>   MIPS: CM: provide a function to map from CPU to VP ID
>   irqchip: mips-gic: convert CPU numbers to VP IDs
>   irqchip: mips-gic: fix pending & mask reads for MIPS64 with 32b GIC

I assume that's a bugfix scheduled for 4.3.

Ralf, if so, please ship it through the MIPS tree with my Acked-by for
the irqchip parts.

Thanks,

	tglx

Re: [PATCH 0/3] MIPS GIC fixes

[Paul Burton]

On Tue, Sep 22, 2015 at 09:07:15PM +0200, Thomas Gleixner wrote:
> On Tue, 22 Sep 2015, Paul Burton wrote:
> 
> > This series fixes a couple of problems with the MIPS GIC support,
> > impacting systems with the 64 bit CM3 and those with multithreading and
> > non-contiguous numbering for VP(E)s across cores.
> > 
> > Paul Burton (3):
> >   MIPS: CM: provide a function to map from CPU to VP ID
> >   irqchip: mips-gic: convert CPU numbers to VP IDs
> >   irqchip: mips-gic: fix pending & mask reads for MIPS64 with 32b GIC
> 
> I assume that's a bugfix scheduled for 4.3.
> 
> Ralf, if so, please ship it through the MIPS tree with my Acked-by for
> the irqchip parts.
> 
> Thanks,
> 
> 	tglx

Hi Thomas,

These are fixes but to the best of my knowledge the only currently
supported system it would break is multicore I6400 on Malta, which only
exists in emulation at the moment. So it's probably not a huge deal to
get this into v4.3. If it's easy though, absolutely go ahead :)

I'll aim to be clearer when submitting future fixes about where they
apply.

Thanks,
    Paul

Re: [PATCH 0/3] MIPS GIC fixes

[Thomas Gleixner]

On Tue, 22 Sep 2015, Paul Burton wrote:
> These are fixes but to the best of my knowledge the only currently
> supported system it would break is multicore I6400 on Malta, which only
> exists in emulation at the moment. So it's probably not a huge deal to
> get this into v4.3. If it's easy though, absolutely go ahead :)
> 
> I'll aim to be clearer when submitting future fixes about where they
> apply.

Please cc me also on the mips part, so I can see the dependencies more
clear.

Thanks,

	tglx