From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934300AbbI1PrI (ORCPT ); Mon, 28 Sep 2015 11:47:08 -0400 Received: from mail-wi0-f178.google.com ([209.85.212.178]:37769 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934209AbbI1PrF (ORCPT ); Mon, 28 Sep 2015 11:47:05 -0400 Date: Mon, 28 Sep 2015 16:47:01 +0100 From: Lee Jones To: Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com, devicetree@vger.kernel.org Subject: Re: [PATCH v2 00/11] Hi Maxime / Patrice / Srini, Message-ID: <20150928154701.GT27197@x1> References: <1443443867-4099-1-git-send-email-peter.griffin@linaro.org> <20150928153938.GS27197@x1> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20150928153938.GS27197@x1> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 28 Sep 2015, Lee Jones wrote: > On Mon, 28 Sep 2015, Peter Griffin wrote: > > > This series makes a series of updates to the stih407 pinctrl groups > > and makes the upstream kernel more closely aligned in terms of pin > > configuration to the vendor kernel. > > > > A number of new periphs are added such as spi fsm, nand, cec0, and > > for others such as SPI the various alternate function pin muxings have > > been added. Finally for SPI the controller nodes have been updated > > to have the default pin assignment in the controller node. > > > > Changes since v1: > > - Rebase on v4.3-rc3 > > - Remove some SoBs (Lee) > > - Collect up Acks > > > > kind regards, > > > > Peter. > > > > Peter Griffin (11): > > ARM: STi: DT: STiH407: Add a cec0 pin definition > > ARM: STi: DT: STiH407: Add i2c3 alternate pin configs > > ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs > > ARM: DT: STiH407: Add serial3 pinctrl configuration > > ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config > > ARM: DT: STiH407: Add NAND flash controller pin configuration > > ARM: DT: STiH407: Add systrace pin configuration > > ARM: DT: STiH407: Add SD pinctrl config for mmc0 controller > > ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX > > ARM: DT: STiH407: Add RMII pinctrl support > > ARM: STi: STiH407: Add spi default pinctrl groups. > > > > arch/arm/boot/dts/stih407-family.dtsi | 14 ++ > > arch/arm/boot/dts/stih407-pinctrl.dtsi | 378 ++++++++++++++++++++++++++++++++- > > 2 files changed, 387 insertions(+), 5 deletions(-) > > I'll do this privately, so as not to unnecessarily delay the > acceptance of the set. Whoops! Fingers faster than brain. Sorry folks. Maxime, Please do not slow up the acceptance of this set due to my comments. > I'm a big fan of keeping the *-by's in chronological order. It does > help to provide an insight to the history of the patch. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog