From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753290AbbJBRTR (ORCPT ); Fri, 2 Oct 2015 13:19:17 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:35975 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752534AbbJBRTQ (ORCPT ); Fri, 2 Oct 2015 13:19:16 -0400 Date: Fri, 2 Oct 2015 18:19:08 +0100 From: Mark Brown To: Jon Ringle Cc: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Message-ID: <20151002171908.GY12635@sirena.org.uk> References: <1443681187-29505-1-git-send-email-jon@ringle.org> <20151001094424.GG15635@sirena.org.uk> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="sKosZo66cxuwvnFI" Content-Disposition: inline In-Reply-To: X-Cookie: Walk softly and carry a megawatt laser. User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: 2a01:348:6:8808:7e7a:91ff:fede:4a45 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH 1/2] regmap: Allow installing custom reg_update_bits function X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --sKosZo66cxuwvnFI Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Oct 01, 2015 at 08:29:19AM -0400, Jon Ringle wrote: > On Thu, 1 Oct 2015, Mark Brown wrote: > > This completely bypasses and therefore breaks the cache infrastructure. > Right after sending the v2 patch, I realized that calling the=20 > custom reg_update_bits would only be applicable for registers that are=20 > marked as volatile. Would the following solution be acceptable (it would= =20 Well, it should still *work* with a cache, though it's certainly true that it's unlikely to have any performance benefit with cached register since the read part of the read/modify/write cycle is essentially free=20 with the cache. > also simplify the regmap_update_bits in the encx24j600 driver): > if (regmap_volatile(map, reg) && map->reg_update_bits) { > return map->reg_update_bits(map->bus_context, reg, mask,=20 > val, change, force_write); > The cache state should not matter for volatile registers, right? Right. I see you've sent a new patch already, I'll reply to that after I've thought about it a little. --sKosZo66cxuwvnFI Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJWDryLAAoJECTWi3JdVIfQ85AH/1N0hojqldZspZOSkngT4+85 +03SYBQHzEpnjlOFk9VrdTppKIKroZKwQQ6S+1PdEG1bdjVioc4Hken0eaHkEFB+ nG+V2Z7yH7+SFydtDR/vLK786RWQVvTvr+k9GJAPer/rHNwknxXy2RPhB4XN+Gvz RZrbps0a+h9qJyHbWROiduRRwtphi4L46H+gR27ZmYvhJ2LzHnuM07piTtMU0u1h hM1ow316B6dZZnc4SqNgX+NstmXT7MB6IECSBHmKrD0xvmTU9I9RnvooQrgFOprN cIYvQe1MHQqvFFMjjIZ/n9WWdhqiV/0JcK6oIc+L8qIXa0OUaZxiM+7Et8O8tgk= =Ox6S -----END PGP SIGNATURE----- --sKosZo66cxuwvnFI--