From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751492AbbJLF6L (ORCPT ); Mon, 12 Oct 2015 01:58:11 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:56302 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751430AbbJLF6C (ORCPT ); Mon, 12 Oct 2015 01:58:02 -0400 Date: Mon, 12 Oct 2015 13:53:50 +0800 From: Jisheng Zhang To: Sebastian Hesselbarth CC: , , Subject: Re: [PATCH RESEND 1/2] arm: berlin: use non-self-cleared reset register to reset cpu Message-ID: <20151012135350.0f127fa3@xhacker> In-Reply-To: <20150921101825.099b304f@xhacker> References: <1442213265-1002-1-git-send-email-jszhang@marvell.com> <1442213265-1002-2-git-send-email-jszhang@marvell.com> <55FEF511.2050600@gmail.com> <20150921101825.099b304f@xhacker> X-Mailer: Claws Mail 3.12.0 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-10-12_03:,, signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510120079 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear Sebastian, On Mon, 21 Sep 2015 10:18:25 +0800 Jisheng Zhang wrote: > Dear Sebastian, > > On Sun, 20 Sep 2015 20:04:01 +0200 > Sebastian Hesselbarth wrote: > > > On 14.09.2015 08:47, Jisheng Zhang wrote: > > > In Berlin SoCs, there are two kinds of cpu reset control registers: the > > > first one's corresponding bits will be self-cleared after some cycles, > > > while the second one's bits won't. Previously the first kind of reset > > > control register is used, this patch uses the second kind one to prepare > > > for the next hotplug commit. > > > > > > Signed-off-by: Jisheng Zhang > > > --- > > > arch/arm/mach-berlin/platsmp.c | 4 +++- > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c > > > index 34a3753..bde327b 100644 > > > --- a/arch/arm/mach-berlin/platsmp.c > > > +++ b/arch/arm/mach-berlin/platsmp.c > > > @@ -17,7 +17,7 @@ > > > #include > > > #include > > > > > > -#define CPU_RESET 0x00 > > > +#define CPU_RESET 0x20 > > > > Jisheng, > > > > I am fine with the patch itself, except that I'd like to rather > > rename the 0x00-register to CPU_RESET_SC with a comment about > > the self-clearing nature. The 0x20-register would then be named > > CPU_RESET_NON_SC and used the way you propose. > > Good idea. And such comment would let people understand why do we change > as that. > > > > > Are you fine with me naming the registers accordingly while > > applying the patches? > > Sure, I'm fine. Thank you very much. I found these two patches are missing in your round 1 berlin pull request. Do you want me send v2 patches applying the above changes you suggested? Thanks, Jisheng > > > > > Sebastian > > > > > #define RESET_VECT 0x00 > > > #define SW_RESET_ADDR 0x94 > > > @@ -31,6 +31,8 @@ static inline void berlin_perform_reset_cpu(unsigned int cpu) > > > u32 val; > > > > > > val = readl(cpu_ctrl + CPU_RESET); > > > + val &= ~BIT(cpu_logical_map(cpu)); > > > + writel(val, cpu_ctrl + CPU_RESET); > > > val |= BIT(cpu_logical_map(cpu)); > > > writel(val, cpu_ctrl + CPU_RESET); > > > } > > > > > >