From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752939AbbJON3j (ORCPT ); Thu, 15 Oct 2015 09:29:39 -0400 Received: from mail-lb0-f169.google.com ([209.85.217.169]:35162 "EHLO mail-lb0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752490AbbJON3i (ORCPT ); Thu, 15 Oct 2015 09:29:38 -0400 Date: Thu, 15 Oct 2015 15:30:01 +0200 From: Christoffer Dall To: "Suzuki K. Poulose" Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, steve.capper@linaro.org, marc.zyngier@arm.com, ard.biesheuvel@linaro.org Subject: Re: [PATCHv3 03/11] arm64: Introduce helpers for page table levels Message-ID: <20151015133001.GF21930@cbox> References: <1444821634-1689-1-git-send-email-suzuki.poulose@arm.com> <1444821634-1689-4-git-send-email-suzuki.poulose@arm.com> <20151015113735.GB21930@cbox> <20151015124451.GI8825@leverpostej> <561FA6AE.6090707@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <561FA6AE.6090707@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 15, 2015 at 02:14:22PM +0100, Suzuki K. Poulose wrote: > On 15/10/15 13:44, Mark Rutland wrote: > >On Thu, Oct 15, 2015 at 01:37:35PM +0200, Christoffer Dall wrote: > >>On Wed, Oct 14, 2015 at 12:20:26PM +0100, Suzuki K. Poulose wrote: > >>>Introduce helpers for finding the number of page table > >>>levels required for a given VA width, shift for a particular > >>>page table level. > > >>>+/* > >>>+ * Size mapped by an entry at level n > >>>+ * We map PAGE_SHIFT - 3 at all levels, except the PAGE_SHIFT bits at the last level > >>>+ */ > >>>+#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3) > >> > >>I feel like I'm partially failing the interview question again, in that > >>I don't fully understand the '+ 3' in the end? > > > >The last level handles PAGE_SHIFT bits (the bits from the VA that are > >the same in the PA). We only accounted for (PAGE_SHIFT - 3) bits at each > >level when multiplying, so we add those 3 missing bits back at the end. > > > > Something like : > > /* > * Size mapped by an entry at level n > * We map PAGE_SHIFT - 3 at all levels, except the last, where we map PAGE_SHIFT bits. > * The maximum number of levels supported by the architecture is 4. Hence at starting > * at level n, we hanve (4 - n) levels of translation. So, the total number of bits nit: s/hanve/have/ > * mapped by an entry at level n is : > * > * ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT > * > * Rearranging it a bit we get : > * (4 - n) * (PAGE_SHIFT - 3) + 3 > */ > > Or we could use the formula without rearranging. > Either way, even I get it now. Thanks for the explanation!! Assuming some version of this goes in: Acked-by: Christoffer Dall