From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932283AbbJUIuY (ORCPT ); Wed, 21 Oct 2015 04:50:24 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([146.101.78.143]:42968 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753705AbbJUIuV convert rfc822-to-8bit (ORCPT ); Wed, 21 Oct 2015 04:50:21 -0400 Date: Wed, 21 Oct 2015 09:50:17 +0100 From: Dave Martin To: "Suzuki K. Poulose" Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, Vladimir.Murzin@arm.com, steve.capper@linaro.org, ryan.arnold@linaro.org, ard.biesheuvel@linaro.org, aph@redhat.com, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, edward.nevill@linaro.org, james.morse@arm.com, andre.przywara@arm.com, marc.zyngier@arm.com, christoffer.dall@linaro.org Subject: Re: [PATCHv4 23/24] arm64: Expose feature registers by emulating MRS Message-ID: <20151021085017.GF4801@e103592.cambridge.arm.com> References: <1445261101-22344-1-git-send-email-suzuki.poulose@arm.com> <1445261101-22344-24-git-send-email-suzuki.poulose@arm.com> MIME-Version: 1.0 In-Reply-To: <1445261101-22344-24-git-send-email-suzuki.poulose@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginalArrivalTime: 21 Oct 2015 08:50:17.0813 (UTC) FILETIME=[82A73850:01D10BDD] X-MC-Unique: 9XQ86Wj5RU63GZ3mk4uOwA-1 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 19, 2015 at 02:25:00PM +0100, Suzuki K. Poulose wrote: > This patch adds the hook for emulating MRS instruction to > export the 'user visible' value of supported system registers. > We emulate only the following id space for system registers: > Op0=0, Op1=0, CRn=0. [...] > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 896a821..c44da31 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c [...] > @@ -908,3 +910,106 @@ void __init setup_cpu_features(void) > pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", > L1_CACHE_BYTES, cls); > } > + > +/* > + * We emulate only the following system register space. > + * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0 - 7] nit: ^ whitespace, no need to fix unless respinning the series [...] > +/* > + * With CRm = 0, id should be one of : > + * MIDR_EL1 > + * MPIDR_EL1 > + * REVIDR_EL1 nit: ^ whitespace [...] Cheers ---Dave