From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932294AbbJUJmG (ORCPT ); Wed, 21 Oct 2015 05:42:06 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:32998 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753037AbbJUJmA convert rfc822-to-8bit (ORCPT ); Wed, 21 Oct 2015 05:42:00 -0400 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT To: Ray Jui , "Stephen Boyd" From: Michael Turquette In-Reply-To: <1445293639-5863-2-git-send-email-rjui@broadcom.com> Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, "Simran Rai" , "Ray Jui" , stable@vger.kernel.org References: <1445293639-5863-1-git-send-email-rjui@broadcom.com> <1445293639-5863-2-git-send-email-rjui@broadcom.com> Message-ID: <20151021094154.20687.68970@quantum> User-Agent: alot/0.3.6 Subject: Re: [PATCH v2] clk: iproc: Fix PLL output frequency calculation Date: Wed, 21 Oct 2015 02:41:54 -0700 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Ray Jui (2015-10-19 15:27:19) > From: Simran Rai > > This patch affects the clocks that use fractional ndivider in their > PLL output frequency calculation. Instead of 2^20 divide factor, the > clock's ndiv integer shift was used. Fixed the bug by replacing ndiv > integer shift with 2^20 factor. > > Signed-off-by: Simran Rai > Signed-off-by: Ray Jui > Reviewed-by: Scott Branden > Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Applied to clk-next. Regards, Mike > --- > drivers/clk/bcm/clk-iproc-pll.c | 13 +++++-------- > 1 file changed, 5 insertions(+), 8 deletions(-) > > diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c > index 2dda4e8..d679ab8 100644 > --- a/drivers/clk/bcm/clk-iproc-pll.c > +++ b/drivers/clk/bcm/clk-iproc-pll.c > @@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, > struct iproc_pll *pll = clk->pll; > const struct iproc_pll_ctrl *ctrl = pll->ctrl; > u32 val; > - u64 ndiv; > - unsigned int ndiv_int, ndiv_frac, pdiv; > + u64 ndiv, ndiv_int, ndiv_frac; > + unsigned int pdiv; > > if (parent_rate == 0) > return 0; > @@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, > val = readl(pll->pll_base + ctrl->ndiv_int.offset); > ndiv_int = (val >> ctrl->ndiv_int.shift) & > bit_mask(ctrl->ndiv_int.width); > - ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift; > + ndiv = ndiv_int << 20; > > if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { > val = readl(pll->pll_base + ctrl->ndiv_frac.offset); > ndiv_frac = (val >> ctrl->ndiv_frac.shift) & > bit_mask(ctrl->ndiv_frac.width); > - > - if (ndiv_frac != 0) > - ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) | > - ndiv_frac; > + ndiv += ndiv_frac; > } > > val = readl(pll->pll_base + ctrl->pdiv.offset); > pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); > > - clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift; > + clk->rate = (ndiv * parent_rate) >> 20; > > if (pdiv == 0) > clk->rate *= 2; > -- > 1.9.1 >