From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932233AbbJVH7X (ORCPT ); Thu, 22 Oct 2015 03:59:23 -0400 Received: from smtp3-g21.free.fr ([212.27.42.3]:9509 "EHLO smtp3-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751626AbbJVH7V convert rfc822-to-8bit (ORCPT ); Thu, 22 Oct 2015 03:59:21 -0400 Date: Thu, 22 Oct 2015 09:58:56 +0200 From: Jean-Francois Moine To: Hans de Goede Cc: Jens Kuske , Maxime Ripard , Chen-Yu Tsai , Mike Turquette , Linus Walleij , Rob Herring , Philipp Zabel , Emilio =?UTF-8?B?TMOzcGV6?= , devicetree@vger.kernel.org, Vishnu Patekar , "Reinder E.N. de Haan" , linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-arm-kernel@lists.infradead.org, zhao_steven@263.net Subject: Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support Message-ID: <20151022095857.50e2330b@OPI2> In-Reply-To: <5627E515.6050505@redhat.com> References: <1445444007-4260-1-git-send-email-jenskuske@gmail.com> <5627E515.6050505@redhat.com> X-Mailer: Claws Mail 3.13.0 (GTK+ 2.24.28; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 21 Oct 2015 21:18:45 +0200 Hans de Goede wrote: > Great to see that you've started working on this again. Last weekend I > ended up working on this too together with Reinder E.N. de Haan > (added to the Cc). > > We took a slightly different approach for the gates clocks, see: > > https://github.com/jwrdegoede/linux-sunxi/commits/sunxi-wip > > And specifically: > > https://github.com/jwrdegoede/linux-sunxi/commit/80a1afe319d5d1a0c426d42e75d37f0c64e8ea0b > > Combined with: > > https://github.com/jwrdegoede/linux-sunxi/commit/d508da5feb5048f6674d6b24b58ac9058fb9d877 > > This deals with the per gate parents the same way the rockchip > clock code does, and it seems to be quite a bit less code then your solution. Here is a simpler patch: diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c index 6ce9118..8fecaeab 100644 --- a/drivers/clk/sunxi/clk-simple-gates.c +++ b/drivers/clk/sunxi/clk-simple-gates.c @@ -35,6 +35,7 @@ static void __init sunxi_simple_gates_setup(struct device_node *node, void __iomem *reg; const __be32 *p; int number, i = 0, j; + bool parent_per_gate; u8 clk_bit; u32 index; @@ -43,6 +44,7 @@ static void __init sunxi_simple_gates_setup(struct device_node *node, return; clk_parent = of_clk_get_parent_name(node, 0); + parent_per_gate = of_clk_get_parent_count(node) != 1; clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); if (!clk_data) @@ -58,6 +60,8 @@ static void __init sunxi_simple_gates_setup(struct device_node *node, of_property_for_each_u32(node, "clock-indices", prop, p, index) { of_property_read_string_index(node, "clock-output-names", i, &clk_name); + if (parent_per_gate) + clk_parent = of_clk_get_parent_name(node, i); clk_reg = reg + 4 * (index / 32); clk_bit = index % 32; -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/