From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752289AbbJYUUS (ORCPT ); Sun, 25 Oct 2015 16:20:18 -0400 Received: from down.free-electrons.com ([37.187.137.238]:33210 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751600AbbJYUUP (ORCPT ); Sun, 25 Oct 2015 16:20:15 -0400 Date: Sun, 25 Oct 2015 21:20:12 +0100 From: Maxime Ripard To: Vishnu Patekar Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, emilio@elopez.com.ar, linus.walleij@linaro.org, jenskuske@gmail.com, hdegoede@redhat.com, wens@csie.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-gpio@vger.kernel.org Subject: Re: [PATCH v2 2/3] ARM: dts: sun8i: Add Allwinner A83T dtsi Message-ID: <20151025202012.GT10947@lukather> References: <1445557577-27383-1-git-send-email-vishnupatekar0510@gmail.com> <1445557577-27383-3-git-send-email-vishnupatekar0510@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="q8laNvmP2d33pnUN" Content-Disposition: inline In-Reply-To: <1445557577-27383-3-git-send-email-vishnupatekar0510@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --q8laNvmP2d33pnUN Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Fri, Oct 23, 2015 at 07:46:16AM +0800, Vishnu Patekar wrote: > + memory { > + reg =3D <0x40000000 0x80000000>; > + }; > + > + timer { > + compatible =3D "arm,armv7-timer"; > + interrupts =3D , > + , > + , > + ; Shouldn't the number of CPUs be 8? > + clock-frequency =3D <24000000>; > + arm,cpu-registers-not-fw-configured; > + }; Is there some u-boot support for this SoC yet? If so, both the memory node and the clock-frequency and arm,cpu-registers-not-fw-configured properties are useless (and harmful for the latter). > + soc@01c00000 { Please remove the address. It's both wrong and useless. > + compatible =3D "simple-bus"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + > + gic: interrupt-controller@01c81000 { > + compatible =3D "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg =3D <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + interrupts =3D ; > + }; > + > + pio: pinctrl@01c20800 { > + compatible =3D "allwinner,sun8i-a83t-pinctrl"; > + interrupts =3D , > + , > + ; Please align these lines with the first one, like you did for the GIC's reg for example. > + reg =3D <0x01c20800 0x400>; > + clocks =3D <&osc24M>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + #gpio-cells =3D <3>; > + > + i2c0_pins_a: i2c0@0 { > + allwinner,pins =3D "PH0", "PH1"; > + allwinner,function =3D "i2c0"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + i2c1_pins_a: i2c1@0 { > + allwinner,pins =3D "PH2", "PH3"; > + allwinner,function =3D "i2c1"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + i2c2_pins_a: i2c2@0 { > + allwinner,pins =3D "PH4", "PH5"; > + allwinner,function =3D "i2c2"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + mmc0_pins_a: mmc0@0 { > + allwinner,pins =3D "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + allwinner,function =3D "mmc0"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + mmc1_pins_a: mmc1@0 { > + allwinner,pins =3D "PG0", "PG1", "PG2", > + "PG3", "PG4", "PG5"; > + allwinner,function =3D "mmc1"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + mmc2_8bit_pins: mmc2_8bit { > + allwinner,pins =3D "PC5", "PC6", "PC8", > + "PC9", "PC10", "PC11", > + "PC12", "PC13", "PC14", > + "PC15"; > + allwinner,function =3D "mmc2"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + uart0_pins_a: uart0@0 { > + allwinner,pins =3D "PF2", "PF4"; > + allwinner,function =3D "uart0"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + uart0_pins_b: uart0@1 { > + allwinner,pins =3D "PB9", "PB10"; > + allwinner,function =3D "uart0"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; Are you going to use all these options? Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --q8laNvmP2d33pnUN Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWLTl7AAoJEBx+YmzsjxAg8YkP/0ozhoi2yIbY8o/YL6UTKBM0 Hv1MF8g3aW55uvMioYzQLfb+e47J+fCHnh1q0Pl3c9ZHRqUyMknz6fEN6b4+1qbQ 9POMNMPHos/xk9Tto24KTSTJtWsGqkxw6kKzmfwowiJonBQMOlH082L4++hdHwih IEMUk1vXzVOtl1AgSSR9l1koYaFSjgyd8TtCXJ1h4GjxTq6kKE0njrI0HydwiqIy BoKkUv1RtSWIskSTrmvxAPsVqTAng8xZJGVG7qDQg1b+iZbnhZH+fQ4xfjqTBFGd sC+DC02xK9Svm2Q7vbZEgiGwOBM7wnznkhb+zL1fVN0APzZiAkxvUIlnW+LwrOJq WEX8PXXsJNiMYSN6xT/78whK1TpNTY56lVfyxFFoZfK16vmfWGZBdDvaY4GIX+SQ KRur3/c6nd67rdUgj8S9wUvDwRDA064BnKjwwUfbNf0eOZuBs1CmDnCFy3OL5e3T gkV8KN19gA+whSfczzSS3tj+qR2QYAhrkXDbBKWWtDm56jgy28dLArsmJx0ijgDJ jggHxHNGupEg7LdkLP4KMqGoYhHDAKk4momAryhrDFcs+pNMbMQW3yO2sFkv9slT rE9EEARMrAaXWupAZHwehuBD17eSStt3wYHV4bWxtZeIFwD+arpWdd+aDTq+sgFW 1v7uZVVcycxYDTfa1TyN =l0DB -----END PGP SIGNATURE----- --q8laNvmP2d33pnUN--