From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964983AbbJ0Qex (ORCPT ); Tue, 27 Oct 2015 12:34:53 -0400 Received: from foss.arm.com ([217.140.101.70]:57436 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932466AbbJ0Qev (ORCPT ); Tue, 27 Oct 2015 12:34:51 -0400 Date: Tue, 27 Oct 2015 16:34:41 +0000 From: Mark Rutland To: "J. German Rivera" Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bhupesh.sharma@freescale.com, stuart.yoder@freescale.com, leoli@freescale.com Subject: Re: [PATCH] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC Message-ID: <20151027163441.GK3091@leverpostej> References: <1445650280-9966-1-git-send-email-German.Rivera@freescale.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1445650280-9966-1-git-send-email-German.Rivera@freescale.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 23, 2015 at 08:31:20PM -0500, J. German Rivera wrote: > Added sys-reboot node to the FSL's LS2085A SoC DT to leverage > the ARM-generic reboot mechanism for this SoC. This mechanism > is enabled through CONFIG_POWER_RESET_SYSCON. Per the comments in arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi, the platform has PSCI 0.2+, and therefore already has system reset functionality. Given that, why is this necessary? Thanks, Mark. > Signed-off-by: J. German Rivera > --- > arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi > index e281ceb..6f82163 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi > @@ -131,6 +131,18 @@ > interrupts = <1 9 0x4>; > }; > > + rst_ccsr: rstccsr@1E60000 { > + compatible = "syscon"; > + reg = <0x0 0x1E60000 0x0 0x10000>; > + }; > + > + reboot@65024000 { > + compatible ="syscon-reboot"; > + regmap = <&rst_ccsr>; > + offset = <0x0>; > + mask = <0x2>; > + }; > + > timer { > compatible = "arm,armv8-timer"; > interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ > -- > 2.3.3 >