[PATCH V2 0/2] Add new features introduced in AMD Fam17h

[PATCH V2 0/2] Add new features introduced in AMD Fam17h

[Aravind Gopalakrishnan]

Patch1: Add Scalable MCA feature identification
Patch2: Add CLZERO feature

Changes in V2: (per Boris)
 - Fix "From" line in Patch2 to reflect correct authorship
 - Sanitize comments a bit.

Note: local tip build failed for me initially. Applied the
      fix proposed here: 
      http://marc.info/?l=linux-kernel&m=144592319708523&w=2
      after which it worked fine.

Aravind Gopalakrishnan (1):
  x86/mcheck: Add Scalable MCA cpuid bit

Wan Zongshun (1):
  x86/cpufeature: Add CLZERO feature

 arch/x86/include/asm/cpufeature.h |  5 ++++-
 arch/x86/include/asm/mce.h        | 13 ++++++++++++-
 arch/x86/kernel/cpu/common.c      |  1 +
 arch/x86/kernel/cpu/mcheck/mce.c  |  2 ++
 4 files changed, 19 insertions(+), 2 deletions(-)

-- 
2.6.1

[PATCH V2 1/2] x86/mcheck: Add Scalable MCA cpuid bit

[Aravind Gopalakrishnan]

Scalable MCA (SMCA) is a new feature in AMD Fam17h
processors which indicates presence of MCA extensions.

MCA extensions expands existing register space for the
MCE banks and also introduces a new MSR range to
accommodate new banks. Future additions to AMD MCE code
will first need to detect if SMCA is enabled before
enabling the new features.

Adding code to detect if it SMCA is enabled in this patch
and store that info in mce_vendor_flags structure.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 arch/x86/include/asm/mce.h       | 13 ++++++++++++-
 arch/x86/kernel/cpu/mcheck/mce.c |  2 ++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2dbc0bf..63307b5 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -135,7 +135,18 @@ struct mce_vendor_flags {
 			 * in HW and deferred error interrupts.
 			 */
 			succor		: 1,
-			__reserved_0	: 62;
+
+			/*
+			 * Scalable MCA: This bit indicates support for MCAX
+			 * (MCA EXtensions) which expands the register space
+			 * for each MCA bank and also increases number of
+			 * banks. Also, to accommodate the new banks and
+			 * registers, the MCA register space is moved to a new
+			 * MSR range
+			 */
+			smca		: 1,
+
+			__reserved_0	: 61;
 };
 extern struct mce_vendor_flags mce_flags;
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 17b5ec6..3d631c4 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1605,6 +1605,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 		mce_amd_feature_init(c);
 		mce_flags.overflow_recov = !!(ebx & BIT(0));
 		mce_flags.succor	 = !!(ebx & BIT(1));
+		mce_flags.smca		 = !!(ebx & BIT(3));
+
 		break;
 		}
 
-- 
2.6.1

[PATCH V2 2/2] x86/cpufeature: Add CLZERO feature

[Aravind Gopalakrishnan]

From: Wan Zongshun <Vincent.Wan@amd.com>

CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.

Add the bit here to allow /proc/cpuinfo to list the feature

Signed-off-by: Wan Zongshun <Vincent.Wan@amd.com>
[Wrap code in patch form, fix comments]
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
---
 arch/x86/include/asm/cpufeature.h | 5 ++++-
 arch/x86/kernel/cpu/common.c      | 1 +
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 9727b3b..e4f8010 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
 #include <asm/disabled-features.h>
 #endif
 
-#define NCAPINTS	13	/* N 32-bit words worth of info */
+#define NCAPINTS	14	/* N 32-bit words worth of info */
 #define NBUGINTS	1	/* N 32-bit bug flags */
 
 /*
@@ -255,6 +255,9 @@
 /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
 #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
 
+/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
+#define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */
+
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index de22ea7..4ddd780 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 
 		c->x86_virt_bits = (eax >> 8) & 0xff;
 		c->x86_phys_bits = eax & 0xff;
+		c->x86_capability[13] = cpuid_ebx(0x80000008);
 	}
 #ifdef CONFIG_X86_32
 	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
-- 
2.6.1

Re: [PATCH V2 1/2] x86/mcheck: Add Scalable MCA cpuid bit

[Borislav Petkov]

On Wed, Oct 28, 2015 at 02:03:29PM -0500, Aravind Gopalakrishnan wrote:
> Scalable MCA (SMCA) is a new feature in AMD Fam17h
> processors which indicates presence of MCA extensions.
> 
> MCA extensions expands existing register space for the
> MCE banks and also introduces a new MSR range to
> accommodate new banks. Future additions to AMD MCE code
> will first need to detect if SMCA is enabled before
> enabling the new features.
> 
> Adding code to detect if it SMCA is enabled in this patch
> and store that info in mce_vendor_flags structure.
> 
> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
> ---
>  arch/x86/include/asm/mce.h       | 13 ++++++++++++-
>  arch/x86/kernel/cpu/mcheck/mce.c |  2 ++
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
> index 2dbc0bf..63307b5 100644
> --- a/arch/x86/include/asm/mce.h
> +++ b/arch/x86/include/asm/mce.h
> @@ -135,7 +135,18 @@ struct mce_vendor_flags {
>  			 * in HW and deferred error interrupts.
>  			 */
>  			succor		: 1,
> -			__reserved_0	: 62;
> +
> +			/*
> +			 * Scalable MCA: This bit indicates support for MCAX
> +			 * (MCA EXtensions) which expands the register space

I changed that to SMCA. Let's refer to this feature with only one
abbreviation please. It seems hw vendors won't settle on names easily so
we should avoid that confusion in the kernel, at least.

Anyway, applied,
thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.