From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030794AbbJ3KUv (ORCPT ); Fri, 30 Oct 2015 06:20:51 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:15005 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756952AbbJ3KUu (ORCPT ); Fri, 30 Oct 2015 06:20:50 -0400 Date: Fri, 30 Oct 2015 18:14:39 +0800 From: Jisheng Zhang To: , CC: , Subject: Re: [PATCH] clocksource: dw_apb_timer_of: support timer-based delay Message-ID: <20151030181439.2b64335c@xhacker> In-Reply-To: <1446193659-1698-1-git-send-email-jszhang@marvell.com> References: <1446193659-1698-1-git-send-email-jszhang@marvell.com> X-Mailer: Claws Mail 3.13.0 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-10-30_08:,, signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510300190 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear Daniel, On Fri, 30 Oct 2015 16:27:39 +0800 Jisheng Zhang wrote: > Implement an ARM delay timer to be used for udelay(). This allows us to > skip the delay loop calibration at boot on Marvell BG2, BG2Q, BG2CD > platforms. And after this patch, udelay() will be unaffected by CPU > frequency changes. The commit msg doesn't follow "clocksource/drivers/...: Dnnn.." But I guess I'll need to post v2, v3 ..., I'll change the msg style in v2. Thanks, Jisheng > > Signed-off-by: Jisheng Zhang > --- > drivers/clocksource/Kconfig | 10 ++++++++++ > drivers/clocksource/dw_apb_timer_of.c | 16 ++++++++++++++++ > 2 files changed, 26 insertions(+) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index a7726db..7b081805 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -29,6 +29,16 @@ config DW_APB_TIMER_OF > select DW_APB_TIMER > select CLKSRC_OF > > +config DW_APB_TIMER_BASED_DELAY > + bool "DW APB timer based delay" > + depends on ARM && DW_APB_TIMER_OF > + default n > + help > + This option enables support for using the DW APB timer to > + implement timer-based delay. It is useful for skiping the > + delay loop calibration at boot on some platforms. And the > + udelay() will be unaffected by CPU frequency changes. > + > config ROCKCHIP_TIMER > bool > select CLKSRC_OF > diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c > index a19a3f6..4bab048 100644 > --- a/drivers/clocksource/dw_apb_timer_of.c > +++ b/drivers/clocksource/dw_apb_timer_of.c > @@ -16,6 +16,7 @@ > * You should have received a copy of the GNU General Public License > * along with this program. If not, see . > */ > +#include > #include > #include > #include > @@ -130,6 +131,17 @@ static void __init init_sched_clock(void) > sched_clock_register(read_sched_clock, 32, sched_rate); > } > > +#ifdef CONFIG_DW_APB_TIMER_BASED_DELAY > +static unsigned long dw_apb_delay_timer_read(void) > +{ > + return ~readl_relaxed(sched_io_base); > +} > + > +static struct delay_timer dw_apb_delay_timer = { > + .read_current_timer = dw_apb_delay_timer_read, > +}; > +#endif > + > static int num_called; > static void __init dw_apb_timer_init(struct device_node *timer) > { > @@ -142,6 +154,10 @@ static void __init dw_apb_timer_init(struct device_node *timer) > pr_debug("%s: found clocksource timer\n", __func__); > add_clocksource(timer); > init_sched_clock(); > +#ifdef CONFIG_DW_APB_TIMER_BASED_DELAY > + dw_apb_delay_timer.freq = sched_rate; > + register_current_timer_delay(&dw_apb_delay_timer); > +#endif > break; > default: > break;