From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1033089AbbKFJQC (ORCPT ); Fri, 6 Nov 2015 04:16:02 -0500 Received: from mga03.intel.com ([134.134.136.65]:54872 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030698AbbKFJP7 (ORCPT ); Fri, 6 Nov 2015 04:15:59 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,251,1444719600"; d="scan'208";a="828973222" Date: Fri, 6 Nov 2015 11:15:55 +0200 From: Mika Westerberg To: Thierry Reding Cc: linux-pwm@vger.kernel.org, Qipeng Zha , Huiquan Zhong , linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Message-ID: <20151106091555.GW1509@lahna.fi.intel.com> References: <1445349187-114759-1-git-send-email-mika.westerberg@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1445349187-114759-1-git-send-email-mika.westerberg@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 20, 2015 at 04:53:05PM +0300, Mika Westerberg wrote: > New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI) > device. Each PWM has 1k of register space allocated from the parent device. > Add support for this. Hi Thierry, Are you going to pick these up to PWM tree? Thanks.