From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161531AbbKFNgV (ORCPT ); Fri, 6 Nov 2015 08:36:21 -0500 Received: from mga14.intel.com ([192.55.52.115]:5917 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161510AbbKFNgT (ORCPT ); Fri, 6 Nov 2015 08:36:19 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,252,1444719600"; d="scan'208";a="595247003" Date: Fri, 6 Nov 2015 15:36:02 +0200 From: Mika Westerberg To: Thierry Reding Cc: linux-pwm@vger.kernel.org, Qipeng Zha , Huiquan Zhong , linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] pwm: lpss: Add support for multiple PWMs Message-ID: <20151106133602.GY1509@lahna.fi.intel.com> References: <1445349187-114759-1-git-send-email-mika.westerberg@linux.intel.com> <20151106132953.GA31797@ulmo> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20151106132953.GA31797@ulmo> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 06, 2015 at 02:29:53PM +0100, Thierry Reding wrote: > On Tue, Oct 20, 2015 at 04:53:05PM +0300, Mika Westerberg wrote: > > New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI) > > device. Each PWM has 1k of register space allocated from the parent device. > > Add support for this. > > > > Signed-off-by: Mika Westerberg > > --- > > drivers/pwm/pwm-lpss.c | 48 +++++++++++++++++++++++++++--------------------- > > drivers/pwm/pwm-lpss.h | 1 + > > 2 files changed, 28 insertions(+), 21 deletions(-) > > Applied all three patches, with a minor cleanup, see below. > > > diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h > > index aa041bb1b67d..ef2419f47c57 100644 > > --- a/drivers/pwm/pwm-lpss.h > > +++ b/drivers/pwm/pwm-lpss.h > > @@ -20,6 +20,7 @@ struct pwm_lpss_chip; > > > > struct pwm_lpss_boardinfo { > > unsigned long clk_rate; > > + size_t npwm; > > }; > > I changed the type of npwm to unsigned int to match the definition of > the pwm_chip.npwm field. Thanks!