From: Peter Zijlstra <peterz@infradead.org>
To: Gratian Crisan <gratian.crisan@ni.com>
Cc: Josh Hunt <joshhunt00@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
LKML <linux-kernel@vger.kernel.org>,
Ingo Molnar <mingo@redhat.com>, "H . Peter Anvin" <hpa@zytor.com>,
x86@kernel.org, Borislav Petkov <bp@alien8.de>,
Josh Cartwright <joshc@ni.com>,
gratian@gmail.com
Subject: Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error
Date: Fri, 13 Nov 2015 21:43:38 +0100 [thread overview]
Message-ID: <20151113204338.GA9928@worktop.ger.corp.intel.com> (raw)
In-Reply-To: <87io58tufu.fsf@spline.amer.corp.natinst.com>
On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote:
> I also wrote a small C utility[1], with a bit of code borrowed from the
> kernel, for reading the TSC on all CPUs. It starts a high priority
> thread per CPU, tries to synchronize them and prints out the TSC values
> and their offset with regards to CPU0.
> It can be called from a SysV init shell script[2] at the beginning of
> the boot process and right before a reboot to save the values in a file.
Could you also read and print TSC_ADJUST (msr 0x3b) ? This would tell us
if for example your BIOS messed it up.
next prev parent reply other threads:[~2015-11-13 20:43 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-09 19:59 [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error gratian.crisan
2015-11-09 22:02 ` Peter Zijlstra
[not found] ` <CAKA=qzarnUUmZb7DQE+u0Dei3F+FQNoL2bak_-dV9D9+3L=itQ@mail.gmail.com>
2015-11-10 18:27 ` Josh Hunt
2015-11-10 19:47 ` Gratian Crisan
2015-11-10 20:41 ` Josh Hunt
2015-11-11 15:41 ` Gratian Crisan
2015-11-13 20:43 ` Peter Zijlstra [this message]
2015-11-17 16:38 ` Gratian Crisan
2015-11-19 19:04 ` Gratian Crisan
2015-11-13 21:13 ` Dave Hansen
2015-11-17 16:49 ` Gratian Crisan
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