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From: Stephen Boyd <sboyd@codeaurora.org>
To: Jon Hunter <jonathanh@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org, Rhyland Klein <rklein@nvidia.com>
Subject: Re: [PATCH] clk: tegra: Fix bypassing of PLLs
Date: Fri, 20 Nov 2015 09:15:27 -0800	[thread overview]
Message-ID: <20151120171527.GL32672@codeaurora.org> (raw)
In-Reply-To: <1448032264-29622-1-git-send-email-jonathanh@nvidia.com>

On 11/20, Jon Hunter wrote:
> The _clk_disable_pll() function will attempt to place a PLL into bypass
> if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL
> by clearing the enable bit. To place the PLL into bypass, the bypass bit
> needs to be set and not cleared. Fix this by setting the bypass bit and
> not clearing it.
> 
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---

Fixes tag? It looks like this has been wrong from the beginning
of time.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  parent reply	other threads:[~2015-11-20 17:15 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-20 15:11 [PATCH] clk: tegra: Fix bypassing of PLLs Jon Hunter
2015-11-20 16:43 ` Rhyland Klein
2015-11-20 17:15 ` Stephen Boyd [this message]
2015-11-23 12:36   ` Jon Hunter
2015-11-23 23:18 ` Tyler Baker
2015-11-24 10:21   ` Jon Hunter
2015-11-24 15:10   ` Thierry Reding
2015-11-24 15:25   ` Jon Hunter
2015-11-25 15:11   ` Thierry Reding
2015-11-25 15:52     ` Tyler Baker
2015-11-25 17:48       ` Jon Hunter
2015-11-26  9:56         ` Jon Hunter

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