From: Stephen Boyd <sboyd@codeaurora.org>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@baylibre.com>,
Chen-Yu Tsai <wens@csie.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH] clk: sunxi: pll2: Fix clock running too fast
Date: Mon, 30 Nov 2015 11:29:46 -0800 [thread overview]
Message-ID: <20151130192946.GH11298@codeaurora.org> (raw)
In-Reply-To: <1448897699-20475-1-git-send-email-maxime.ripard@free-electrons.com>
On 11/30, Maxime Ripard wrote:
> Contrary to what the datasheet says, the pre divider doesn't seem to be
> incremented by one in the PLL2, but just uses the value from the register,
> with 0 being a bypass.
>
> This fixes the audio playing too fast.
>
> Since we now have the same pre-divider flags, and the only difference with
> the A10 is the post-divider offset, also remove the structure to just pass
> the offset as an argument.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>
> Hi Stephen, Mike,
>
> Could you apply this patch for 4.4?
>
I take it this should have a
Fixes: eb662f854710 ("clk: sunxi: pll2: Add A13 support")
attached to it?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-11-30 19:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-30 15:34 [PATCH] clk: sunxi: pll2: Fix clock running too fast Maxime Ripard
2015-11-30 19:29 ` Stephen Boyd [this message]
2015-11-30 19:32 ` Stephen Boyd
2015-11-30 20:14 ` Maxime Ripard
2015-11-30 19:42 ` kbuild test robot
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