From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757300AbbLCHb1 (ORCPT ); Thu, 3 Dec 2015 02:31:27 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:53155 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751745AbbLCHbZ (ORCPT ); Thu, 3 Dec 2015 02:31:25 -0500 Date: Wed, 2 Dec 2015 23:31:23 -0800 From: Stephen Boyd To: Maxime Ripard Cc: Mike Turquette , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v2] clk: sunxi: pll2: Fix clock running too fast Message-ID: <20151203073123.GD14699@codeaurora.org> References: <1448968492-28979-1-git-send-email-maxime.ripard@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1448968492-28979-1-git-send-email-maxime.ripard@free-electrons.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/01, Maxime Ripard wrote: > Contrary to what the datasheet says, the pre divider doesn't seem to be > incremented by one in the PLL2, but just uses the value from the register, > with 0 being a bypass. > > This fixes the audio playing too fast. > > Since we now have the same pre-divider flags, and the only difference with > the A10 is the post-divider offset, also remove the structure to just pass > the offset as an argument. > > Signed-off-by: Maxime Ripard > --- Applied to clk-fixes + I added the Fixes tag. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project