From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933099AbbLHIiF (ORCPT ); Tue, 8 Dec 2015 03:38:05 -0500 Received: from bombadil.infradead.org ([198.137.202.9]:35007 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933094AbbLHIiD (ORCPT ); Tue, 8 Dec 2015 03:38:03 -0500 Date: Tue, 8 Dec 2015 09:37:57 +0100 From: Peter Zijlstra To: Harish Chegondi Cc: linux-kernel@vger.kernel.org, mingo@redhat.com, Harish Chegondi , Andi Kleen , Kan Liang , Lukasz Anaczkowski Subject: Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing Message-ID: <20151208083757.GD6356@twins.programming.kicks-ass.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2012-12-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote: > Knights Landing core is based on Silvermont core with several differences. > Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the > LBR MSRs addresses match those of the Xeon cores' first 8 pairs of LBR MSRs > +/* Knights Landing */ > +void intel_pmu_lbr_init_knl(void) > +{ > + x86_pmu.lbr_nr = 8; > + x86_pmu.lbr_tos = MSR_LBR_TOS; > + x86_pmu.lbr_from = MSR_LBR_NHM_FROM; > + x86_pmu.lbr_to = MSR_LBR_NHM_TO; > + > + x86_pmu.lbr_sel_mask = LBR_SEL_MASK; > + x86_pmu.lbr_sel_map = snb_lbr_sel_map; Also, unlike Silvermont, this thing seems to have hardware LBR filters. So would it not be more accurate to say the KNL has a big core LBR instead? (Note that this LBR setup isn't specific to Xeon's, all of the Core chips have this, including the client parts). > + pr_cont("8-deep LBR, "); > +}