From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752100AbcADIdo (ORCPT ); Mon, 4 Jan 2016 03:33:44 -0500 Received: from down.free-electrons.com ([37.187.137.238]:34768 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751274AbcADIdm (ORCPT ); Mon, 4 Jan 2016 03:33:42 -0500 Date: Mon, 4 Jan 2016 09:33:39 +0100 From: Boris Brezillon To: Milo Kim Cc: , , , , , , Subject: Re: [PATCH 05/19] irqchip: atmel-aic: use simple constant to get number of interrupts per chip Message-ID: <20160104093339.7df4605f@bbrezillon> In-Reply-To: <1451881723-2478-6-git-send-email-milo.kim@ti.com> References: <1451881723-2478-1-git-send-email-milo.kim@ti.com> <1451881723-2478-6-git-send-email-milo.kim@ti.com> X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.27; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 4 Jan 2016 13:28:29 +0900 Milo Kim wrote: > Number of interrupts per each chip is determined when IRQ controller > allocates IRQ chip by calling irq_alloc_domain_generic_chips(). > This number is fixed by atmel-aic-common part. The value is 32. > So each AIC driver can use this value directly in IRQ chip operation. Sorry, but I don't like the idea of hardcoding the number of irqs per chip just to optimize some functions that are rarely called. What if atmel creates a chip using the AIC but exposing less than 32 irqs? You'll have to change all those places. Do you have a strong reason to do this kind of optimization? > > Cc: Thomas Gleixner > Cc: Jason Cooper > Cc: Marc Zyngier > Cc: Alexandre Belloni > Cc: Boris BREZILLON > Cc: Ludovic Desroches > Cc: Nicolas Ferre > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Milo Kim > --- > drivers/irqchip/irq-atmel-aic.c | 2 +- > drivers/irqchip/irq-atmel-aic5.c | 9 +++------ > 2 files changed, 4 insertions(+), 7 deletions(-) > > diff --git a/drivers/irqchip/irq-atmel-aic.c b/drivers/irqchip/irq-atmel-aic.c > index c499949..f2c0fd9 100644 > --- a/drivers/irqchip/irq-atmel-aic.c > +++ b/drivers/irqchip/irq-atmel-aic.c > @@ -188,7 +188,7 @@ static int aic_irq_domain_xlate(struct irq_domain *d, > if (ret) > return ret; > > - idx = intspec[0] / dgc->irqs_per_chip; > + idx = intspec[0] / AIC_IRQS_PER_CHIP; > if (idx >= dgc->num_chips) > return -EINVAL; > > diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c > index f5848c8..50d540b 100644 > --- a/drivers/irqchip/irq-atmel-aic5.c > +++ b/drivers/irqchip/irq-atmel-aic5.c > @@ -153,14 +153,13 @@ static int aic5_set_type(struct irq_data *d, unsigned type) > static void aic5_suspend(struct irq_data *d) > { > struct irq_domain *domain = d->domain; > - struct irq_domain_chip_generic *dgc = domain->gc; > struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); > struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); > int i; > u32 mask; > > irq_gc_lock(bgc); > - for (i = 0; i < dgc->irqs_per_chip; i++) { > + for (i = 0; i < AIC_IRQS_PER_CHIP; i++) { > mask = 1 << i; > if ((mask & gc->mask_cache) == (mask & gc->wake_active)) > continue; > @@ -177,14 +176,13 @@ static void aic5_suspend(struct irq_data *d) > static void aic5_resume(struct irq_data *d) > { > struct irq_domain *domain = d->domain; > - struct irq_domain_chip_generic *dgc = domain->gc; > struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); > struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); > int i; > u32 mask; > > irq_gc_lock(bgc); > - for (i = 0; i < dgc->irqs_per_chip; i++) { > + for (i = 0; i < AIC_IRQS_PER_CHIP; i++) { > mask = 1 << i; > if ((mask & gc->mask_cache) == (mask & gc->wake_active)) > continue; > @@ -201,13 +199,12 @@ static void aic5_resume(struct irq_data *d) > static void aic5_pm_shutdown(struct irq_data *d) > { > struct irq_domain *domain = d->domain; > - struct irq_domain_chip_generic *dgc = domain->gc; > struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); > struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); > int i; > > irq_gc_lock(bgc); > - for (i = 0; i < dgc->irqs_per_chip; i++) { > + for (i = 0; i < AIC_IRQS_PER_CHIP; i++) { > irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR); > irq_reg_writel(bgc, 1, AT91_AIC5_IDCR); > irq_reg_writel(bgc, 1, AT91_AIC5_ICCR); -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com